00001 /********************************************************************* 00002 * 00003 * Filename: nsc_fir.h 00004 * Version: 00005 * Description: 00006 * Status: Experimental. 00007 * Author: Dag Brattli <dagb@cs.uit.no> 00008 * Created at: Fri Nov 13 14:37:40 1998 00009 * Modified at: Tue Jan 11 10:19:50 2000 00010 * Modified by: Dag Brattli <dagb@cs.uit.no> 00011 * 00012 * Copyright (c) 1998-2000 Dag Brattli <dagb@cs.uit.no> 00013 * Copyright (c) 1998 Lichen Wang, <lwang@actisys.com> 00014 * Copyright (c) 1998 Actisys Corp., www.actisys.com 00015 * All Rights Reserved 00016 * 00017 * This program is free software; you can redistribute it and/or 00018 * modify it under the terms of the GNU General Public License as 00019 * published by the Free Software Foundation; either version 2 of 00020 * the License, or (at your option) any later version. 00021 * 00022 * Neither Dag Brattli nor University of Tromsų admit liability nor 00023 * provide warranty for any of this software. This material is 00024 * provided "AS-IS" and at no charge. 00025 * 00026 ********************************************************************/ 00027 00028 #ifndef NSC_IRCC_H 00029 #define NSC_IRCC_H 00030 00031 #include <linux/time.h> 00032 00033 #include <asm/spinlock.h> 00034 #include <asm/io.h> 00035 00036 #define PC87108 0x10 00037 #define PC97338 0xb0 00038 00039 /* DMA modes needed */ 00040 #define DMA_TX_MODE 0x08 /* Mem to I/O, ++, demand. */ 00041 #define DMA_RX_MODE 0x04 /* I/O to mem, ++, demand. */ 00042 00043 /* Flags for configuration register CRF0 */ 00044 #define APEDCRC 0x02 00045 #define ENBNKSEL 0x01 00046 00047 /* Set 0 */ 00048 #define TXD 0x00 /* Transmit data port */ 00049 #define RXD 0x00 /* Receive data port */ 00050 00051 /* Register 1 */ 00052 #define IER 0x01 /* Interrupt Enable Register*/ 00053 #define IER_RXHDL_IE 0x01 /* Receiver high data level interrupt */ 00054 #define IER_TXLDL_IE 0x02 /* Transeiver low data level interrupt */ 00055 #define IER_LS_IE 0x04//* Link Status Interrupt */ 00056 #define IER_ETXURI 0x04 /* Tx underrun */ 00057 #define IER_DMA_IE 0x10 /* DMA finished interrupt */ 00058 #define IER_TXEMP_IE 0x20 00059 #define IER_SFIF_IE 0x40 /* Frame status FIFO intr */ 00060 #define IER_TMR_IE 0x80 /* Timer event */ 00061 00062 #define FCR 0x02 /* (write only) */ 00063 #define FCR_FIFO_EN 0x01 /* Enable FIFO's */ 00064 #define FCR_RXSR 0x02 /* Rx FIFO soft reset */ 00065 #define FCR_TXSR 0x04 /* Tx FIFO soft reset */ 00066 #define FCR_RXTH 0x40 /* Rx FIFO threshold (set to 16) */ 00067 #define FCR_TXTH 0x20 /* Tx FIFO threshold (set to 17) */ 00068 00069 #define EIR 0x02 /* (read only) */ 00070 #define EIR_RXHDL_EV 0x01 00071 #define EIR_TXLDL_EV 0x02 00072 #define EIR_LS_EV 0x04 00073 #define EIR_DMA_EV 0x10 00074 #define EIR_TXEMP_EV 0x20 00075 #define EIR_SFIF_EV 0x40 00076 #define EIR_TMR_EV 0x80 00077 00078 #define LCR 0x03 /* Link control register */ 00079 #define LCR_WLS_8 0x03 /* 8 bits */ 00080 00081 #define BSR 0x03 /* Bank select register */ 00082 #define BSR_BKSE 0x80 00083 #define BANK0 LCR_WLS_8 /* Must make sure that we set 8N1 */ 00084 #define BANK1 0x80 00085 #define BANK2 0xe0 00086 #define BANK3 0xe4 00087 #define BANK4 0xe8 00088 #define BANK5 0xec 00089 #define BANK6 0xf0 00090 #define BANK7 0xf4 00091 00092 #define MCR 0x04 /* Mode Control Register */ 00093 #define MCR_MODE_MASK ~(0xd0) 00094 #define MCR_UART 0x00 00095 #define MCR_RESERVED 0x20 00096 #define MCR_SHARP_IR 0x40 00097 #define MCR_SIR 0x60 00098 #define MCR_MIR 0x80 00099 #define MCR_FIR 0xa0 00100 #define MCR_CEIR 0xb0 00101 #define MCR_IR_PLS 0x10 00102 #define MCR_DMA_EN 0x04 00103 #define MCR_EN_IRQ 0x08 00104 #define MCR_TX_DFR 0x08 00105 00106 #define LSR 0x05 /* Link status register */ 00107 #define LSR_RXDA 0x01 /* Receiver data available */ 00108 #define LSR_TXRDY 0x20 /* Transmitter ready */ 00109 #define LSR_TXEMP 0x40 /* Transmitter empty */ 00110 00111 #define ASCR 0x07 /* Auxillary Status and Control Register */ 00112 #define ASCR_RXF_TOUT 0x01 /* Rx FIFO timeout */ 00113 #define ASCR_FEND_INF 0x02 /* Frame end bytes in rx FIFO */ 00114 #define ASCR_S_EOT 0x04 /* Set end of transmission */ 00115 #define ASCT_RXBSY 0x20 /* Rx busy */ 00116 #define ASCR_TXUR 0x40 /* Transeiver underrun */ 00117 #define ASCR_CTE 0x80 /* Clear timer event */ 00118 00119 /* Bank 2 */ 00120 #define BGDL 0x00 /* Baud Generator Divisor Port (Low Byte) */ 00121 #define BGDH 0x01 /* Baud Generator Divisor Port (High Byte) */ 00122 00123 #define ECR1 0x02 /* Extended Control Register 1 */ 00124 #define ECR1_EXT_SL 0x01 /* Extended Mode Select */ 00125 #define ECR1_DMANF 0x02 /* DMA Fairness */ 00126 #define ECR1_DMATH 0x04 /* DMA Threshold */ 00127 #define ECR1_DMASWP 0x08 /* DMA Swap */ 00128 00129 #define EXCR2 0x04 00130 #define EXCR2_TFSIZ 0x01 /* Rx FIFO size = 32 */ 00131 #define EXCR2_RFSIZ 0x04 /* Tx FIFO size = 32 */ 00132 00133 #define TXFLV 0x06 /* Tx FIFO level */ 00134 #define RXFLV 0x07 /* Rx FIFO level */ 00135 00136 /* Bank 3 */ 00137 #define MID 0x00 00138 00139 /* Bank 4 */ 00140 #define TMRL 0x00 /* Timer low byte */ 00141 #define TMRH 0x01 /* Timer high byte */ 00142 #define IRCR1 0x02 /* Infrared control register 1 */ 00143 #define IRCR1_TMR_EN 0x01 /* Timer enable */ 00144 00145 #define TFRLL 0x04 00146 #define TFRLH 0x05 00147 #define RFRLL 0x06 00148 #define RFRLH 0x07 00149 00150 /* Bank 5 */ 00151 #define IRCR2 0x04 /* Infrared control register 2 */ 00152 #define IRCR2_MDRS 0x04 /* MIR data rate select */ 00153 #define IRCR2_FEND_MD 0x20 /* */ 00154 00155 #define FRM_ST 0x05 /* Frame status FIFO */ 00156 #define FRM_ST_VLD 0x80 /* Frame status FIFO data valid */ 00157 #define FRM_ST_ERR_MSK 0x5f 00158 #define FRM_ST_LOST_FR 0x40 /* Frame lost */ 00159 #define FRM_ST_MAX_LEN 0x10 /* Max frame len exceeded */ 00160 #define FRM_ST_PHY_ERR 0x08 /* Physical layer error */ 00161 #define FRM_ST_BAD_CRC 0x04 00162 #define FRM_ST_OVR1 0x02 /* Rx FIFO overrun */ 00163 #define FRM_ST_OVR2 0x01 /* Frame status FIFO overrun */ 00164 00165 #define RFLFL 0x06 00166 #define RFLFH 0x07 00167 00168 /* Bank 6 */ 00169 #define IR_CFG2 0x00 00170 #define IR_CFG2_DIS_CRC 0x02 00171 00172 /* Bank 7 */ 00173 #define IRM_CR 0x07 /* Infrared module control register */ 00174 #define IRM_CR_IRX_MSL 0x40 00175 #define IRM_CR_AF_MNT 0x80 /* Automatic format */ 00176 00177 /* For storing entries in the status FIFO */ 00178 struct st_fifo_entry { 00179 int status; 00180 int len; 00181 }; 00182 00183 struct st_fifo { 00184 struct st_fifo_entry entries[10]; 00185 int head; 00186 int tail; 00187 int len; 00188 }; 00189 00190 struct frame_cb { 00191 void *start; /* Start of frame in DMA mem */ 00192 int len; /* Lenght of frame in DMA mem */ 00193 }; 00194 00195 #define MAX_WINDOW 7 00196 00197 struct tx_fifo { 00198 struct frame_cb queue[MAX_WINDOW]; /* Info about frames in queue */ 00199 int ptr; /* Currently being sent */ 00200 int len; /* Lenght of queue */ 00201 int free; /* Next free slot */ 00202 void *tail; /* Next free start in DMA mem */ 00203 }; 00204 00205 /* Private data for each instance */ 00206 struct nsc_ircc_cb { 00207 struct st_fifo st_fifo; /* Info about received frames */ 00208 struct tx_fifo tx_fifo; /* Info about frames to be transmitted */ 00209 00210 int tx_buff_offsets[10]; /* Offsets between frames in tx_buff */ 00211 int tx_len; /* Number of frames in tx_buff */ 00212 00213 struct device *netdev; /* Yes! we are some kind of netdevice */ 00214 struct net_device_stats stats; 00215 00216 struct irlap_cb *irlap; /* The link layer we are binded to */ 00217 00218 struct chipio_t io; /* IrDA controller information */ 00219 struct iobuff_t tx_buff; /* Transmit buffer */ 00220 struct iobuff_t rx_buff; /* Receive buffer */ 00221 struct qos_info qos; /* QoS capabilities for this device */ 00222 00223 struct timeval stamp; 00224 struct timeval now; 00225 00226 spinlock_t lock; /* For serializing operations */ 00227 00228 __u32 flags; /* Interface flags */ 00229 __u32 new_speed; 00230 int suspend; 00231 }; 00232 00233 static inline void switch_bank(int iobase, int bank) 00234 { 00235 outb(bank, iobase+BSR); 00236 } 00237 00238 #endif /* NSC_IRCC_H */