00001 /********************************************************************* 00002 * 00003 * Filename: nsc-ircc.h 00004 * Version: 00005 * Description: 00006 * Status: Experimental. 00007 * Author: Dag Brattli <dagb@cs.uit.no> 00008 * Created at: Fri Nov 13 14:37:40 1998 00009 * Modified at: Sun Jan 23 17:47:00 2000 00010 * Modified by: Dag Brattli <dagb@cs.uit.no> 00011 * 00012 * Copyright (c) 1998-2000 Dag Brattli <dagb@cs.uit.no> 00013 * Copyright (c) 1998 Lichen Wang, <lwang@actisys.com> 00014 * Copyright (c) 1998 Actisys Corp., www.actisys.com 00015 * All Rights Reserved 00016 * 00017 * This program is free software; you can redistribute it and/or 00018 * modify it under the terms of the GNU General Public License as 00019 * published by the Free Software Foundation; either version 2 of 00020 * the License, or (at your option) any later version. 00021 * 00022 * Neither Dag Brattli nor University of Tromsų admit liability nor 00023 * provide warranty for any of this software. This material is 00024 * provided "AS-IS" and at no charge. 00025 * 00026 ********************************************************************/ 00027 00028 #ifndef NSC_IRCC_H 00029 #define NSC_IRCC_H 00030 00031 #include <linux/time.h> 00032 00033 #include <asm/spinlock.h> 00034 #include <asm/io.h> 00035 00036 /* DMA modes needed */ 00037 #define DMA_TX_MODE 0x08 /* Mem to I/O, ++, demand. */ 00038 #define DMA_RX_MODE 0x04 /* I/O to mem, ++, demand. */ 00039 00040 /* Config registers for the '108 */ 00041 #define CFG_BAIC 0x00 00042 #define CFG_CSRT 0x01 00043 #define CFG_MCTL 0x02 00044 00045 /* Config registers for the '338 */ 00046 #define CFG_FER 0x00 00047 #define CFG_FAR 0x01 00048 #define CFG_PTR 0x02 00049 #define CFG_PNP0 0x1b 00050 #define CFG_PNP1 0x1c 00051 #define CFG_PNP3 0x4f 00052 00053 /* Flags for configuration register CRF0 */ 00054 #define APEDCRC 0x02 00055 #define ENBNKSEL 0x01 00056 00057 /* Set 0 */ 00058 #define TXD 0x00 /* Transmit data port */ 00059 #define RXD 0x00 /* Receive data port */ 00060 00061 /* Register 1 */ 00062 #define IER 0x01 /* Interrupt Enable Register*/ 00063 #define IER_RXHDL_IE 0x01 /* Receiver high data level interrupt */ 00064 #define IER_TXLDL_IE 0x02 /* Transeiver low data level interrupt */ 00065 #define IER_LS_IE 0x04//* Link Status Interrupt */ 00066 #define IER_ETXURI 0x04 /* Tx underrun */ 00067 #define IER_DMA_IE 0x10 /* DMA finished interrupt */ 00068 #define IER_TXEMP_IE 0x20 00069 #define IER_SFIF_IE 0x40 /* Frame status FIFO intr */ 00070 #define IER_TMR_IE 0x80 /* Timer event */ 00071 00072 #define FCR 0x02 /* (write only) */ 00073 #define FCR_FIFO_EN 0x01 /* Enable FIFO's */ 00074 #define FCR_RXSR 0x02 /* Rx FIFO soft reset */ 00075 #define FCR_TXSR 0x04 /* Tx FIFO soft reset */ 00076 #define FCR_RXTH 0x40 /* Rx FIFO threshold (set to 16) */ 00077 #define FCR_TXTH 0x20 /* Tx FIFO threshold (set to 17) */ 00078 00079 #define EIR 0x02 /* (read only) */ 00080 #define EIR_RXHDL_EV 0x01 00081 #define EIR_TXLDL_EV 0x02 00082 #define EIR_LS_EV 0x04 00083 #define EIR_DMA_EV 0x10 00084 #define EIR_TXEMP_EV 0x20 00085 #define EIR_SFIF_EV 0x40 00086 #define EIR_TMR_EV 0x80 00087 00088 #define LCR 0x03 /* Link control register */ 00089 #define LCR_WLS_8 0x03 /* 8 bits */ 00090 00091 #define BSR 0x03 /* Bank select register */ 00092 #define BSR_BKSE 0x80 00093 #define BANK0 LCR_WLS_8 /* Must make sure that we set 8N1 */ 00094 #define BANK1 0x80 00095 #define BANK2 0xe0 00096 #define BANK3 0xe4 00097 #define BANK4 0xe8 00098 #define BANK5 0xec 00099 #define BANK6 0xf0 00100 #define BANK7 0xf4 00101 00102 #define MCR 0x04 /* Mode Control Register */ 00103 #define MCR_MODE_MASK ~(0xd0) 00104 #define MCR_UART 0x00 00105 #define MCR_RESERVED 0x20 00106 #define MCR_SHARP_IR 0x40 00107 #define MCR_SIR 0x60 00108 #define MCR_MIR 0x80 00109 #define MCR_FIR 0xa0 00110 #define MCR_CEIR 0xb0 00111 #define MCR_IR_PLS 0x10 00112 #define MCR_DMA_EN 0x04 00113 #define MCR_EN_IRQ 0x08 00114 #define MCR_TX_DFR 0x08 00115 00116 #define LSR 0x05 /* Link status register */ 00117 #define LSR_RXDA 0x01 /* Receiver data available */ 00118 #define LSR_TXRDY 0x20 /* Transmitter ready */ 00119 #define LSR_TXEMP 0x40 /* Transmitter empty */ 00120 00121 #define ASCR 0x07 /* Auxillary Status and Control Register */ 00122 #define ASCR_RXF_TOUT 0x01 /* Rx FIFO timeout */ 00123 #define ASCR_FEND_INF 0x02 /* Frame end bytes in rx FIFO */ 00124 #define ASCR_S_EOT 0x04 /* Set end of transmission */ 00125 #define ASCT_RXBSY 0x20 /* Rx busy */ 00126 #define ASCR_TXUR 0x40 /* Transeiver underrun */ 00127 #define ASCR_CTE 0x80 /* Clear timer event */ 00128 00129 /* Bank 2 */ 00130 #define BGDL 0x00 /* Baud Generator Divisor Port (Low Byte) */ 00131 #define BGDH 0x01 /* Baud Generator Divisor Port (High Byte) */ 00132 00133 #define ECR1 0x02 /* Extended Control Register 1 */ 00134 #define ECR1_EXT_SL 0x01 /* Extended Mode Select */ 00135 #define ECR1_DMANF 0x02 /* DMA Fairness */ 00136 #define ECR1_DMATH 0x04 /* DMA Threshold */ 00137 #define ECR1_DMASWP 0x08 /* DMA Swap */ 00138 00139 #define EXCR2 0x04 00140 #define EXCR2_TFSIZ 0x01 /* Rx FIFO size = 32 */ 00141 #define EXCR2_RFSIZ 0x04 /* Tx FIFO size = 32 */ 00142 00143 #define TXFLV 0x06 /* Tx FIFO level */ 00144 #define RXFLV 0x07 /* Rx FIFO level */ 00145 00146 /* Bank 3 */ 00147 #define MID 0x00 00148 00149 /* Bank 4 */ 00150 #define TMRL 0x00 /* Timer low byte */ 00151 #define TMRH 0x01 /* Timer high byte */ 00152 #define IRCR1 0x02 /* Infrared control register 1 */ 00153 #define IRCR1_TMR_EN 0x01 /* Timer enable */ 00154 00155 #define TFRLL 0x04 00156 #define TFRLH 0x05 00157 #define RFRLL 0x06 00158 #define RFRLH 0x07 00159 00160 /* Bank 5 */ 00161 #define IRCR2 0x04 /* Infrared control register 2 */ 00162 #define IRCR2_MDRS 0x04 /* MIR data rate select */ 00163 #define IRCR2_FEND_MD 0x20 /* */ 00164 00165 #define FRM_ST 0x05 /* Frame status FIFO */ 00166 #define FRM_ST_VLD 0x80 /* Frame status FIFO data valid */ 00167 #define FRM_ST_ERR_MSK 0x5f 00168 #define FRM_ST_LOST_FR 0x40 /* Frame lost */ 00169 #define FRM_ST_MAX_LEN 0x10 /* Max frame len exceeded */ 00170 #define FRM_ST_PHY_ERR 0x08 /* Physical layer error */ 00171 #define FRM_ST_BAD_CRC 0x04 00172 #define FRM_ST_OVR1 0x02 /* Rx FIFO overrun */ 00173 #define FRM_ST_OVR2 0x01 /* Frame status FIFO overrun */ 00174 00175 #define RFLFL 0x06 00176 #define RFLFH 0x07 00177 00178 /* Bank 6 */ 00179 #define IR_CFG2 0x00 00180 #define IR_CFG2_DIS_CRC 0x02 00181 00182 /* Bank 7 */ 00183 #define IRM_CR 0x07 /* Infrared module control register */ 00184 #define IRM_CR_IRX_MSL 0x40 00185 #define IRM_CR_AF_MNT 0x80 /* Automatic format */ 00186 00187 /* NSC chip information */ 00188 struct nsc_chip { 00189 char *name; /* Name of chipset */ 00190 int cfg[3]; /* Config registers */ 00191 u_int8_t cid_index; /* Chip identification index reg */ 00192 u_int8_t cid_value; /* Chip identification expected value */ 00193 u_int8_t cid_mask; /* Chip identification revision mask */ 00194 00195 /* Functions for probing and initializing the specific chip */ 00196 int (*probe)(struct nsc_chip *chip, chipio_t *info); 00197 int (*init)(struct nsc_chip *chip, chipio_t *info); 00198 }; 00199 typedef struct nsc_chip nsc_chip_t; 00200 00201 /* For storing entries in the status FIFO */ 00202 struct st_fifo_entry { 00203 int status; 00204 int len; 00205 }; 00206 00207 #define MAX_TX_WINDOW 7 00208 #define MAX_RX_WINDOW 7 00209 00210 struct st_fifo { 00211 struct st_fifo_entry entries[MAX_RX_WINDOW]; 00212 int pending_bytes; 00213 int head; 00214 int tail; 00215 int len; 00216 }; 00217 00218 struct frame_cb { 00219 void *start; /* Start of frame in DMA mem */ 00220 int len; /* Lenght of frame in DMA mem */ 00221 }; 00222 00223 struct tx_fifo { 00224 struct frame_cb queue[MAX_TX_WINDOW]; /* Info about frames in queue */ 00225 int ptr; /* Currently being sent */ 00226 int len; /* Lenght of queue */ 00227 int free; /* Next free slot */ 00228 void *tail; /* Next free start in DMA mem */ 00229 }; 00230 00231 /* Private data for each instance */ 00232 struct nsc_ircc_cb { 00233 struct st_fifo st_fifo; /* Info about received frames */ 00234 struct tx_fifo tx_fifo; /* Info about frames to be transmitted */ 00235 00236 struct device *netdev; /* Yes! we are some kind of netdevice */ 00237 struct net_device_stats stats; 00238 00239 struct irlap_cb *irlap; /* The link layer we are binded to */ 00240 struct qos_info qos; /* QoS capabilities for this device */ 00241 00242 chipio_t io; /* IrDA controller information */ 00243 iobuff_t tx_buff; /* Transmit buffer */ 00244 iobuff_t rx_buff; /* Receive buffer */ 00245 00246 __u8 ier; /* Interrupt enable register */ 00247 00248 struct timeval stamp; 00249 struct timeval now; 00250 00251 spinlock_t lock; /* For serializing operations */ 00252 00253 __u32 flags; /* Interface flags */ 00254 __u32 new_speed; 00255 int index; /* Instance index */ 00256 }; 00257 00258 static inline void switch_bank(int iobase, int bank) 00259 { 00260 outb(bank, iobase+BSR); 00261 } 00262 00263 #endif /* NSC_IRCC_H */