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00083 #undef MATROXFB_DEBUG
00084
00085
00086
00087 #undef MATROXFB_DEBUG_HEAVY
00088
00089
00090
00091 #undef MATROXFB_DEBUG_LOOP
00092
00093
00094 #undef MATROXFB_DEBUG_REG
00095
00096
00097 #undef MATROXFB_DEBUG_REENTER
00098
00099 #undef MATROXFB_DEBUG_CONSOLEBH
00100
00101 #include <linux/config.h>
00102 #include <linux/module.h>
00103 #include <linux/kernel.h>
00104 #include <linux/errno.h>
00105 #include <linux/string.h>
00106 #include <linux/mm.h>
00107 #include <linux/tty.h>
00108 #include <linux/malloc.h>
00109 #include <linux/delay.h>
00110 #include <linux/fb.h>
00111 #include <linux/console.h>
00112 #include <linux/selection.h>
00113 #include <linux/ioport.h>
00114 #include <linux/init.h>
00115 #include <linux/timer.h>
00116 #include <linux/pci.h>
00117
00118 #include <asm/io.h>
00119 #include <asm/spinlock.h>
00120 #include <asm/unaligned.h>
00121 #ifdef CONFIG_MTRR
00122 #include <asm/mtrr.h>
00123 #endif
00124
00125 #include <video/fbcon.h>
00126 #include <video/fbcon-cfb4.h>
00127 #include <video/fbcon-cfb8.h>
00128 #include <video/fbcon-cfb16.h>
00129 #include <video/fbcon-cfb24.h>
00130 #include <video/fbcon-cfb32.h>
00131
00132 #if defined(CONFIG_FB_OF)
00133 #if defined(CONFIG_FB_COMPAT_XPMAC)
00134 #include <asm/vc_ioctl.h>
00135 #endif
00136 #include <asm/prom.h>
00137 #include <asm/pci-bridge.h>
00138 #include <video/macmodes.h>
00139 #endif
00140
00141
00142 #define CONFIG_FB_MATROX_32MB
00143
00144 #define FBCON_HAS_VGATEXT
00145
00146 #ifdef MATROXFB_DEBUG
00147
00148 #define DEBUG
00149 #define DBG(x) printk(KERN_DEBUG "matroxfb: %s\n", (x));
00150
00151 #ifdef MATROXFB_DEBUG_HEAVY
00152 #define DBG_HEAVY(x) DBG(x)
00153 #else
00154 #define DBG_HEAVY(x)
00155 #endif
00156
00157 #ifdef MATROXFB_DEBUG_LOOP
00158 #define DBG_LOOP(x) DBG(x)
00159 #else
00160 #define DBG_LOOP(x)
00161 #endif
00162
00163 #ifdef MATROXFB_DEBUG_REG
00164 #define DBG_REG(x) DBG(x)
00165 #else
00166 #define DBG_REG(x)
00167 #endif
00168
00169 #else
00170
00171 #define DBG(x)
00172 #define DBG_HEAVY(x)
00173 #define DBG_REG(x)
00174 #define DBG_LOOP(x)
00175
00176 #endif
00177
00178 #ifndef __i386__
00179 #ifndef ioremap_nocache
00180 #define ioremap_nocache(X,Y) ioremap(X,Y)
00181 #endif
00182 #endif
00183
00184 #if defined(__alpha__) || defined(__m68k__)
00185 #define READx_WORKS
00186 #define MEMCPYTOIO_WORKS
00187 #else
00188 #define READx_FAILS
00189
00190
00191
00192
00193 #if defined(__i386__)
00194 #define MEMCPYTOIO_MEMCPY
00195 #else
00196 #define MEMCPYTOIO_WRITEL
00197 #endif
00198 #endif
00199
00200 #ifdef __sparc__
00201 #error "Sorry, I have no idea how to do this on sparc... There is mapioaddr... With bus_type parameter..."
00202 #endif
00203
00204 #if defined(__m68k__)
00205 #define MAP_BUSTOVIRT
00206 #else
00207 #define MAP_IOREMAP
00208 #endif
00209
00210 #ifdef DEBUG
00211 #define dprintk(X...) printk(X)
00212 #else
00213 #define dprintk(X...)
00214 #endif
00215
00216 #ifndef PCI_SS_VENDOR_ID_SIEMENS_NIXDORF
00217 #define PCI_SS_VENDOR_ID_SIEMENS_NIXDORF 0x110A
00218 #endif
00219 #ifndef PCI_SS_VENDOR_ID_MATROX
00220 #define PCI_SS_VENDOR_ID_MATROX PCI_VENDOR_ID_MATROX
00221 #endif
00222 #ifndef PCI_DEVICE_ID_MATROX_G200_PCI
00223 #define PCI_DEVICE_ID_MATROX_G200_PCI 0x0520
00224 #endif
00225 #ifndef PCI_DEVICE_ID_MATROX_G200_AGP
00226 #define PCI_DEVICE_ID_MATROX_G200_AGP 0x0521
00227 #endif
00228 #ifndef PCI_DEVICE_ID_MATROX_G100
00229 #define PCI_DEVICE_ID_MATROX_G100 0x1000
00230 #endif
00231 #ifndef PCI_DEVICE_ID_MATROX_G100_AGP
00232 #define PCI_DEVICE_ID_MATROX_G100_AGP 0x1001
00233 #endif
00234 #ifndef PCI_DEVICE_ID_MATROX_G400_AGP
00235 #define PCI_DEVICE_ID_MATROX_G400_AGP 0x0525
00236 #endif
00237
00238 #ifndef PCI_SS_ID_MATROX_PRODUCTIVA_G100_AGP
00239 #define PCI_SS_ID_MATROX_GENERIC 0xFF00
00240 #define PCI_SS_ID_MATROX_PRODUCTIVA_G100_AGP 0xFF01
00241 #define PCI_SS_ID_MATROX_MYSTIQUE_G200_AGP 0xFF02
00242 #define PCI_SS_ID_MATROX_MILLENIUM_G200_AGP 0xFF03
00243 #define PCI_SS_ID_MATROX_MARVEL_G200_AGP 0xFF04
00244 #define PCI_SS_ID_MATROX_MGA_G100_PCI 0xFF05
00245 #define PCI_SS_ID_MATROX_MGA_G100_AGP 0x1001
00246 #define PCI_SS_ID_SIEMENS_MGA_G100_AGP 0x001E
00247 #define PCI_SS_ID_SIEMENS_MGA_G200_AGP 0x0032
00248 #endif
00249
00250 #define MX_VISUAL_TRUECOLOR FB_VISUAL_DIRECTCOLOR
00251 #define MX_VISUAL_DIRECTCOLOR FB_VISUAL_TRUECOLOR
00252 #define MX_VISUAL_PSEUDOCOLOR FB_VISUAL_PSEUDOCOLOR
00253
00254 #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
00255
00256
00257 #undef NEED_DAC1064
00258 #if defined(CONFIG_FB_MATROX_MYSTIQUE) || defined(CONFIG_FB_MATROX_G100)
00259 #define NEED_DAC1064 1
00260 #endif
00261
00262 typedef struct {
00263 u_int8_t* vaddr;
00264 } vaddr_t;
00265
00266 #ifdef READx_WORKS
00267 static inline unsigned int mga_readb(vaddr_t va, unsigned int offs) {
00268 return readb(va.vaddr + offs);
00269 }
00270
00271 static inline unsigned int mga_readw(vaddr_t va, unsigned int offs) {
00272 return readw(va.vaddr + offs);
00273 }
00274
00275 static inline u_int32_t mga_readl(vaddr_t va, unsigned int offs) {
00276 return readl(va.vaddr + offs);
00277 }
00278
00279 static inline void mga_writeb(vaddr_t va, unsigned int offs, u_int8_t value) {
00280 writeb(value, va.vaddr + offs);
00281 }
00282
00283 static inline void mga_writew(vaddr_t va, unsigned int offs, u_int16_t value) {
00284 writew(value, va.vaddr + offs);
00285 }
00286
00287 static inline void mga_writel(vaddr_t va, unsigned int offs, u_int32_t value) {
00288 writel(value, va.vaddr + offs);
00289 }
00290 #else
00291 static inline unsigned int mga_readb(vaddr_t va, unsigned int offs) {
00292 return *(volatile u_int8_t*)(va.vaddr + offs);
00293 }
00294
00295 static inline unsigned int mga_readw(vaddr_t va, unsigned int offs) {
00296 return *(volatile u_int16_t*)(va.vaddr + offs);
00297 }
00298
00299 static inline u_int32_t mga_readl(vaddr_t va, unsigned int offs) {
00300 return *(volatile u_int32_t*)(va.vaddr + offs);
00301 }
00302
00303 static inline void mga_writeb(vaddr_t va, unsigned int offs, u_int8_t value) {
00304 *(volatile u_int8_t*)(va.vaddr + offs) = value;
00305 }
00306
00307 static inline void mga_writew(vaddr_t va, unsigned int offs, u_int16_t value) {
00308 *(volatile u_int16_t*)(va.vaddr + offs) = value;
00309 }
00310
00311 static inline void mga_writel(vaddr_t va, unsigned int offs, u_int32_t value) {
00312 *(volatile u_int32_t*)(va.vaddr + offs) = value;
00313 }
00314 #endif
00315
00316 static inline void mga_memcpy_toio(vaddr_t va, unsigned int offs, const void* src, int len) {
00317 #ifdef MEMCPYTOIO_WORKS
00318 memcpy_toio(va.vaddr + offs, src, len);
00319 #elif defined(MEMCPYTOIO_WRITEL)
00320 #define srcd ((const u_int32_t*)src)
00321 if (offs & 3) {
00322 while (len >= 4) {
00323 mga_writel(va, offs, get_unaligned(srcd++));
00324 offs += 4;
00325 len -= 4;
00326 }
00327 } else {
00328 while (len >= 4) {
00329 mga_writel(va, offs, *srcd++);
00330 offs += 4;
00331 len -= 4;
00332 }
00333 }
00334 #undef srcd
00335 if (len) {
00336 u_int32_t tmp;
00337
00338 memcpy(&tmp, src, len);
00339 mga_writel(va, offs, tmp);
00340 }
00341 #elif defined(MEMCPYTOIO_MEMCPY)
00342 memcpy(va.vaddr + offs, src, len);
00343 #else
00344 #error "Sorry, do not know how to write block of data to device"
00345 #endif
00346 }
00347
00348 static inline void vaddr_add(vaddr_t* va, unsigned long offs) {
00349 va->vaddr += offs;
00350 }
00351
00352 static inline void* vaddr_va(vaddr_t va) {
00353 return va.vaddr;
00354 }
00355
00356 #define MGA_IOREMAP_NORMAL 0
00357 #define MGA_IOREMAP_NOCACHE 1
00358
00359 #define MGA_IOREMAP_FB MGA_IOREMAP_NOCACHE
00360 #define MGA_IOREMAP_MMIO MGA_IOREMAP_NOCACHE
00361 static inline int mga_ioremap(unsigned long phys, unsigned long size, int flags, vaddr_t* virt) {
00362 #ifdef MAP_IOREMAP
00363 if (flags & MGA_IOREMAP_NOCACHE)
00364 virt->vaddr = ioremap_nocache(phys, size);
00365 else
00366 virt->vaddr = ioremap(phys, size);
00367 #else
00368 #ifdef MAP_BUSTOVIRT
00369 virt->vaddr = bus_to_virt(phys);
00370 #else
00371 #error "Your architecture does not have neither ioremap nor bus_to_virt... Giving up"
00372 #endif
00373 #endif
00374 return (virt->vaddr == 0);
00375 }
00376
00377 static inline void mga_iounmap(vaddr_t va) {
00378 #ifdef MAP_IOREMAP
00379 iounmap(va.vaddr);
00380 #endif
00381 }
00382
00383 struct matroxfb_par
00384 {
00385 unsigned int final_bppShift;
00386 unsigned int cmap_len;
00387 struct {
00388 unsigned int bytes;
00389 unsigned int pixels;
00390 unsigned int chunks;
00391 } ydstorg;
00392 void (*putc)(u_int32_t, u_int32_t, struct display*, int, int, int);
00393 void (*putcs)(u_int32_t, u_int32_t, struct display*, const unsigned short*, int, int, int);
00394 };
00395
00396 struct my_timming {
00397 unsigned int pixclock;
00398 unsigned int HDisplay;
00399 unsigned int HSyncStart;
00400 unsigned int HSyncEnd;
00401 unsigned int HTotal;
00402 unsigned int VDisplay;
00403 unsigned int VSyncStart;
00404 unsigned int VSyncEnd;
00405 unsigned int VTotal;
00406 unsigned int sync;
00407 int dblscan;
00408 int interlaced;
00409 };
00410
00411 struct matrox_fb_info;
00412
00413 #define MATROX_2MB_WITH_4MB_ADDON
00414
00415 struct matrox_pll_features {
00416 unsigned int vco_freq_min;
00417 unsigned int ref_freq;
00418 unsigned int feed_div_min;
00419 unsigned int feed_div_max;
00420 unsigned int in_div_min;
00421 unsigned int in_div_max;
00422 unsigned int post_shift_max;
00423 };
00424
00425 struct matrox_DAC1064_features {
00426 u_int8_t xvrefctrl;
00427 unsigned int cursorimage;
00428 };
00429
00430 struct matrox_accel_features {
00431 int has_cacheflush;
00432 };
00433
00434
00435 struct matrox_hw_state {
00436 u_int32_t MXoptionReg;
00437 unsigned char DACclk[6];
00438 unsigned char DACreg[64];
00439 unsigned char MiscOutReg;
00440 unsigned char DACpal[768];
00441 unsigned char CRTC[25];
00442 unsigned char CRTCEXT[9];
00443 unsigned char SEQ[5];
00444
00445 unsigned char GCTL[9];
00446
00447 unsigned char ATTR[21];
00448 };
00449
00450 struct matrox_accel_data {
00451 #ifdef CONFIG_FB_MATROX_MILLENIUM
00452 unsigned char ramdac_rev;
00453 #endif
00454 u_int32_t m_dwg_rect;
00455 u_int32_t m_opmode;
00456 };
00457
00458 #ifdef CONFIG_FB_MATROX_MULTIHEAD
00459 #define ACCESS_FBINFO2(info, x) (info->x)
00460 #define ACCESS_FBINFO(x) ACCESS_FBINFO2(minfo,x)
00461
00462 #define MINFO minfo
00463
00464 #define WPMINFO struct matrox_fb_info* minfo,
00465 #define CPMINFO const struct matrox_fb_info* minfo,
00466 #define PMINFO minfo,
00467
00468 static inline struct matrox_fb_info* mxinfo(const struct display* p) {
00469 return (struct matrox_fb_info*)p->fb_info;
00470 }
00471
00472 #define PMXINFO(p) mxinfo(p),
00473 #define MINFO_FROM(x) struct matrox_fb_info* minfo = x
00474 #define MINFO_FROM_DISP(x) MINFO_FROM(mxinfo(x))
00475
00476 #else
00477
00478 struct matrox_fb_info global_mxinfo;
00479 struct display global_disp;
00480
00481 #define ACCESS_FBINFO(x) (global_mxinfo.x)
00482 #define ACCESS_FBINFO2(info, x) (global_mxinfo.x)
00483
00484 #define MINFO (&global_mxinfo)
00485
00486 #define WPMINFO
00487 #define CPMINFO
00488 #define PMINFO
00489
00490 #if 0
00491 static inline struct matrox_fb_info* mxinfo(const struct display* p) {
00492 return &global_mxinfo;
00493 }
00494 #endif
00495
00496 #define PMXINFO(p)
00497 #define MINFO_FROM(x)
00498 #define MINFO_FROM_DISP(x)
00499
00500 #endif
00501
00502 struct matrox_switch {
00503 int (*preinit)(WPMINFO struct matrox_hw_state*);
00504 void (*reset)(WPMINFO struct matrox_hw_state*);
00505 int (*init)(CPMINFO struct matrox_hw_state*, struct my_timming*, struct display*);
00506 void (*restore)(WPMINFO struct matrox_hw_state*, struct matrox_hw_state*, struct display*);
00507 };
00508
00509 struct matrox_fb_info {
00510
00511 struct fb_info fbcon;
00512
00513 struct matrox_fb_info* next_fb;
00514
00515 struct matroxfb_par curr;
00516 struct matrox_hw_state hw1;
00517 struct matrox_hw_state hw2;
00518 struct matrox_hw_state* newhw;
00519 struct matrox_hw_state* currenthw;
00520
00521 struct matrox_accel_data accel;
00522
00523 struct pci_dev* pcidev;
00524
00525 struct {
00526 unsigned long base;
00527 vaddr_t vbase;
00528 unsigned int len;
00529 unsigned int len_usable;
00530 } video;
00531
00532 struct {
00533 unsigned long base;
00534 vaddr_t vbase;
00535 unsigned int len;
00536 } mmio;
00537
00538 unsigned int max_pixel_clock;
00539
00540 struct matrox_switch* hw_switch;
00541 int currcon;
00542 struct display* currcon_display;
00543
00544 struct {
00545 struct matrox_pll_features pll;
00546 struct matrox_DAC1064_features DAC1064;
00547 struct matrox_accel_features accel;
00548 } features;
00549 struct {
00550 spinlock_t DAC;
00551 } lock;
00552
00553 int interleave;
00554 int millenium;
00555 int milleniumII;
00556 struct {
00557 int cfb4;
00558 const int* vxres;
00559 int cross4MB;
00560 int text;
00561 int plnwt;
00562 } capable;
00563 struct {
00564 unsigned int size;
00565 unsigned int mgabase;
00566 vaddr_t vbase;
00567 } fastfont;
00568 #ifdef CONFIG_MTRR
00569 struct {
00570 int vram;
00571 int vram_valid;
00572 } mtrr;
00573 #endif
00574 struct {
00575 int precise_width;
00576 int mga_24bpp_fix;
00577 int novga;
00578 int nobios;
00579 int nopciretry;
00580 int noinit;
00581 int inverse;
00582 int hwcursor;
00583 int blink;
00584 int sgram;
00585 #ifdef CONFIG_FB_MATROX_32MB
00586 int support32MB;
00587 #endif
00588
00589 int accelerator;
00590 int text_type_aux;
00591 int video64bits;
00592 unsigned int vgastep;
00593 unsigned int textmode;
00594 unsigned int textstep;
00595 unsigned int textvram;
00596 unsigned int ydstorg;
00597
00598 } devflags;
00599 struct display_switch dispsw;
00600 struct {
00601 int x;
00602 int y;
00603 unsigned int w;
00604 unsigned int u;
00605 unsigned int d;
00606 unsigned int type;
00607 int state;
00608 int redraw;
00609 struct timer_list timer;
00610 } cursor;
00611 #if defined(FBCON_HAS_CFB16) || defined(FBCON_HAS_CFB24) || defined(FBCON_HAS_CFB32)
00612 union {
00613 #ifdef FBCON_HAS_CFB16
00614 u_int16_t cfb16[16];
00615 #endif
00616 #ifdef FBCON_HAS_CFB24
00617 u_int32_t cfb24[16];
00618 #endif
00619 #ifdef FBCON_HAS_CFB32
00620 u_int32_t cfb32[16];
00621 #endif
00622 } cmap;
00623 #endif
00624 struct { unsigned red, green, blue, transp; } palette[256];
00625 #if defined(CONFIG_FB_OF) && defined(CONFIG_FB_COMPAT_XPMAC)
00626 char matrox_name[32];
00627 #endif
00628 };
00629
00630 #if defined(CONFIG_FB_OF)
00631 unsigned char nvram_read_byte(int);
00632 int matrox_of_init(struct device_node *dp);
00633 static int default_vmode = VMODE_NVRAM;
00634 static int default_cmode = CMODE_NVRAM;
00635 #endif
00636
00637 #define curr_ydstorg(x) ACCESS_FBINFO2(x, curr.ydstorg.pixels)
00638
00639 #define PCI_OPTION_REG 0x40
00640 #define PCI_MGA_INDEX 0x44
00641 #define PCI_MGA_DATA 0x48
00642
00643 #define M_DWGCTL 0x1C00
00644 #define M_MACCESS 0x1C04
00645 #define M_CTLWTST 0x1C08
00646
00647 #define M_PLNWT 0x1C1C
00648
00649 #define M_BCOL 0x1C20
00650 #define M_FCOL 0x1C24
00651
00652 #define M_SGN 0x1C58
00653 #define M_LEN 0x1C5C
00654 #define M_AR0 0x1C60
00655 #define M_AR1 0x1C64
00656 #define M_AR2 0x1C68
00657 #define M_AR3 0x1C6C
00658 #define M_AR4 0x1C70
00659 #define M_AR5 0x1C74
00660 #define M_AR6 0x1C78
00661
00662 #define M_CXBNDRY 0x1C80
00663 #define M_FXBNDRY 0x1C84
00664 #define M_YDSTLEN 0x1C88
00665 #define M_PITCH 0x1C8C
00666 #define M_YDST 0x1C90
00667 #define M_YDSTORG 0x1C94
00668 #define M_YTOP 0x1C98
00669 #define M_YBOT 0x1C9C
00670
00671
00672 #define M_CACHEFLUSH 0x1FFF
00673
00674 #define M_EXEC 0x0100
00675
00676 #define M_DWG_TRAP 0x04
00677 #define M_DWG_BITBLT 0x08
00678 #define M_DWG_ILOAD 0x09
00679
00680 #define M_DWG_LINEAR 0x0080
00681 #define M_DWG_SOLID 0x0800
00682 #define M_DWG_ARZERO 0x1000
00683 #define M_DWG_SGNZERO 0x2000
00684 #define M_DWG_SHIFTZERO 0x4000
00685
00686 #define M_DWG_REPLACE 0x000C0000
00687 #define M_DWG_REPLACE2 (M_DWG_REPLACE | 0x40)
00688 #define M_DWG_XOR 0x00060010
00689
00690 #define M_DWG_BFCOL 0x04000000
00691 #define M_DWG_BMONOWF 0x08000000
00692
00693 #define M_DWG_TRANSC 0x40000000
00694
00695 #define M_FIFOSTATUS 0x1E10
00696 #define M_STATUS 0x1E14
00697
00698 #define M_IEN 0x1E1C
00699
00700 #define M_VCOUNT 0x1E20
00701
00702 #define M_RESET 0x1E40
00703
00704 #define M_AGP2PLL 0x1E4C
00705
00706 #define M_OPMODE 0x1E54
00707 #define M_OPMODE_DMA_GEN_WRITE 0x00
00708 #define M_OPMODE_DMA_BLIT 0x04
00709 #define M_OPMODE_DMA_VECTOR_WRITE 0x08
00710 #define M_OPMODE_DMA_LE 0x0000
00711 #define M_OPMODE_DMA_BE_8BPP 0x0000
00712 #define M_OPMODE_DMA_BE_16BPP 0x0100
00713 #define M_OPMODE_DMA_BE_32BPP 0x0200
00714 #define M_OPMODE_DIR_LE 0x000000
00715 #define M_OPMODE_DIR_BE_8BPP 0x000000
00716 #define M_OPMODE_DIR_BE_16BPP 0x010000
00717 #define M_OPMODE_DIR_BE_32BPP 0x020000
00718
00719 #define M_ATTR_INDEX 0x1FC0
00720 #define M_ATTR_DATA 0x1FC1
00721
00722 #define M_MISC_REG 0x1FC2
00723 #define M_3C2_RD 0x1FC2
00724
00725 #define M_SEQ_INDEX 0x1FC4
00726 #define M_SEQ_DATA 0x1FC5
00727
00728 #define M_MISC_REG_READ 0x1FCC
00729
00730 #define M_GRAPHICS_INDEX 0x1FCE
00731 #define M_GRAPHICS_DATA 0x1FCF
00732
00733 #define M_CRTC_INDEX 0x1FD4
00734
00735 #define M_ATTR_RESET 0x1FDA
00736 #define M_3DA_WR 0x1FDA
00737
00738 #define M_EXTVGA_INDEX 0x1FDE
00739 #define M_EXTVGA_DATA 0x1FDF
00740
00741
00742 #define M_SRCORG 0x2CB4
00743
00744 #define M_RAMDAC_BASE 0x3C00
00745
00746
00747 #define M_DAC_REG (M_RAMDAC_BASE+0)
00748 #define M_DAC_VAL (M_RAMDAC_BASE+1)
00749 #define M_PALETTE_MASK (M_RAMDAC_BASE+2)
00750
00751 #define M_X_INDEX 0x00
00752 #define M_X_DATAREG 0x0A
00753
00754 #define DAC_XGENIOCTRL 0x2A
00755 #define DAC_XGENIODATA 0x2B
00756
00757 #ifdef CONFIG_FB_MATROX_MILLENIUM
00758 #define TVP3026_INDEX 0x00
00759 #define TVP3026_PALWRADD 0x00
00760 #define TVP3026_PALDATA 0x01
00761 #define TVP3026_PIXRDMSK 0x02
00762 #define TVP3026_PALRDADD 0x03
00763 #define TVP3026_CURCOLWRADD 0x04
00764 #define TVP3026_CLOVERSCAN 0x00
00765 #define TVP3026_CLCOLOR0 0x01
00766 #define TVP3026_CLCOLOR1 0x02
00767 #define TVP3026_CLCOLOR2 0x03
00768 #define TVP3026_CURCOLDATA 0x05
00769 #define TVP3026_CURCOLRDADD 0x07
00770 #define TVP3026_CURCTRL 0x09
00771 #define TVP3026_X_DATAREG 0x0A
00772 #define TVP3026_CURRAMDATA 0x0B
00773 #define TVP3026_CURPOSXL 0x0C
00774 #define TVP3026_CURPOSXH 0x0D
00775 #define TVP3026_CURPOSYL 0x0E
00776 #define TVP3026_CURPOSYH 0x0F
00777
00778 #define TVP3026_XSILICONREV 0x01
00779 #define TVP3026_XCURCTRL 0x06
00780 #define TVP3026_XCURCTRL_DIS 0x00
00781 #define TVP3026_XCURCTRL_3COLOR 0x01
00782 #define TVP3026_XCURCTRL_XGA 0x02
00783 #define TVP3026_XCURCTRL_XWIN 0x03
00784 #define TVP3026_XCURCTRL_BLANK2048 0x00
00785 #define TVP3026_XCURCTRL_BLANK4096 0x10
00786 #define TVP3026_XCURCTRL_INTERLACED 0x20
00787 #define TVP3026_XCURCTRL_ODD 0x00
00788 #define TVP3026_XCURCTRL_EVEN 0x40
00789 #define TVP3026_XCURCTRL_INDIRECT 0x00
00790 #define TVP3026_XCURCTRL_DIRECT 0x80
00791 #define TVP3026_XLATCHCTRL 0x0F
00792 #define TVP3026_XLATCHCTRL_1_1 0x06
00793 #define TVP3026_XLATCHCTRL_2_1 0x07
00794 #define TVP3026_XLATCHCTRL_4_1 0x06
00795 #define TVP3026_XLATCHCTRL_8_1 0x06
00796 #define TVP3026_XLATCHCTRL_16_1 0x06
00797 #define TVP3026A_XLATCHCTRL_4_3 0x06
00798 #define TVP3026A_XLATCHCTRL_8_3 0x07
00799 #define TVP3026B_XLATCHCTRL_4_3 0x08
00800 #define TVP3026B_XLATCHCTRL_8_3 0x06
00801 #define TVP3026_XTRUECOLORCTRL 0x18
00802 #define TVP3026_XTRUECOLORCTRL_VRAM_SHIFT_ACCEL 0x00
00803 #define TVP3026_XTRUECOLORCTRL_VRAM_SHIFT_TVP 0x20
00804 #define TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR 0x80
00805 #define TVP3026_XTRUECOLORCTRL_TRUECOLOR 0x40
00806 #define TVP3026_XTRUECOLORCTRL_DIRECTCOLOR 0x00
00807 #define TVP3026_XTRUECOLORCTRL_24_ALTERNATE 0x08
00808 #define TVP3026_XTRUECOLORCTRL_RGB_888 0x16
00809 #define TVP3026_XTRUECOLORCTRL_BGR_888 0x17
00810 #define TVP3026_XTRUECOLORCTRL_ORGB_8888 0x06
00811 #define TVP3026_XTRUECOLORCTRL_BGRO_8888 0x07
00812 #define TVP3026_XTRUECOLORCTRL_RGB_565 0x05
00813 #define TVP3026_XTRUECOLORCTRL_ORGB_1555 0x04
00814 #define TVP3026_XTRUECOLORCTRL_RGB_664 0x03
00815 #define TVP3026_XTRUECOLORCTRL_RGBO_4444 0x01
00816 #define TVP3026_XMUXCTRL 0x19
00817 #define TVP3026_XMUXCTRL_MEMORY_8BIT 0x01
00818 #define TVP3026_XMUXCTRL_MEMORY_16BIT 0x02
00819 #define TVP3026_XMUXCTRL_MEMORY_32BIT 0x03
00820 #define TVP3026_XMUXCTRL_MEMORY_64BIT 0x04
00821 #define TVP3026_XMUXCTRL_PIXEL_4BIT 0x40
00822 #define TVP3026_XMUXCTRL_PIXEL_4BIT_SWAPPED 0x60
00823 #define TVP3026_XMUXCTRL_PIXEL_8BIT 0x48
00824 #define TVP3026_XMUXCTRL_PIXEL_16BIT 0x50
00825 #define TVP3026_XMUXCTRL_PIXEL_32BIT 0x58
00826 #define TVP3026_XMUXCTRL_VGA 0x98
00827 #define TVP3026_XCLKCTRL 0x1A
00828 #define TVP3026_XCLKCTRL_DIV1 0x00
00829 #define TVP3026_XCLKCTRL_DIV2 0x10
00830 #define TVP3026_XCLKCTRL_DIV4 0x20
00831 #define TVP3026_XCLKCTRL_DIV8 0x30
00832 #define TVP3026_XCLKCTRL_DIV16 0x40
00833 #define TVP3026_XCLKCTRL_DIV32 0x50
00834 #define TVP3026_XCLKCTRL_DIV64 0x60
00835 #define TVP3026_XCLKCTRL_CLKSTOPPED 0x70
00836 #define TVP3026_XCLKCTRL_SRC_CLK0 0x00
00837 #define TVP3026_XCLKCTRL_SRC_CLK1 0x01
00838 #define TVP3026_XCLKCTRL_SRC_CLK2 0x02
00839 #define TVP3026_XCLKCTRL_SRC_NCLK2 0x03
00840 #define TVP3026_XCLKCTRL_SRC_ECLK2 0x04
00841 #define TVP3026_XCLKCTRL_SRC_PLL 0x05
00842 #define TVP3026_XCLKCTRL_SRC_DIS 0x06
00843 #define TVP3026_XCLKCTRL_SRC_CLK0VGA 0x07
00844 #define TVP3026_XPALETTEPAGE 0x1C
00845 #define TVP3026_XGENCTRL 0x1D
00846 #define TVP3026_XGENCTRL_HSYNC_POS 0x00
00847 #define TVP3026_XGENCTRL_HSYNC_NEG 0x01
00848 #define TVP3026_XGENCTRL_VSYNC_POS 0x00
00849 #define TVP3026_XGENCTRL_VSYNC_NEG 0x02
00850 #define TVP3026_XGENCTRL_LITTLE_ENDIAN 0x00
00851 #define TVP3026_XGENCTRL_BIG_ENDIAN 0x08
00852 #define TVP3026_XGENCTRL_BLACK_0IRE 0x00
00853 #define TVP3026_XGENCTRL_BLACK_75IRE 0x10
00854 #define TVP3026_XGENCTRL_NO_SYNC_ON_GREEN 0x00
00855 #define TVP3026_XGENCTRL_SYNC_ON_GREEN 0x20
00856 #define TVP3026_XGENCTRL_OVERSCAN_DIS 0x00
00857 #define TVP3026_XGENCTRL_OVERSCAN_EN 0x40
00858 #define TVP3026_XMISCCTRL 0x1E
00859 #define TVP3026_XMISCCTRL_DAC_PUP 0x00
00860 #define TVP3026_XMISCCTRL_DAC_PDOWN 0x01
00861 #define TVP3026_XMISCCTRL_DAC_EXT 0x00
00862 #define TVP3026_XMISCCTRL_DAC_6BIT 0x04
00863 #define TVP3026_XMISCCTRL_DAC_8BIT 0x0C
00864 #define TVP3026_XMISCCTRL_PSEL_DIS 0x00
00865 #define TVP3026_XMISCCTRL_PSEL_EN 0x10
00866 #define TVP3026_XMISCCTRL_PSEL_LOW 0x00
00867 #define TVP3026_XMISCCTRL_PSEL_HIGH 0x20
00868 #define TVP3026_XGENIOCTRL 0x2A
00869 #define TVP3026_XGENIODATA 0x2B
00870 #define TVP3026_XPLLADDR 0x2C
00871 #define TVP3026_XPLLADDR_X(LOOP,MCLK,PIX) (((LOOP)<<4) | ((MCLK)<<2) | (PIX))
00872 #define TVP3026_XPLLDATA_N 0x00
00873 #define TVP3026_XPLLDATA_M 0x01
00874 #define TVP3026_XPLLDATA_P 0x02
00875 #define TVP3026_XPLLDATA_STAT 0x03
00876 #define TVP3026_XPIXPLLDATA 0x2D
00877 #define TVP3026_XMEMPLLDATA 0x2E
00878 #define TVP3026_XLOOPPLLDATA 0x2F
00879 #define TVP3026_XCOLKEYOVRMIN 0x30
00880 #define TVP3026_XCOLKEYOVRMAX 0x31
00881 #define TVP3026_XCOLKEYREDMIN 0x32
00882 #define TVP3026_XCOLKEYREDMAX 0x33
00883 #define TVP3026_XCOLKEYGREENMIN 0x34
00884 #define TVP3026_XCOLKEYGREENMAX 0x35
00885 #define TVP3026_XCOLKEYBLUEMIN 0x36
00886 #define TVP3026_XCOLKEYBLUEMAX 0x37
00887 #define TVP3026_XCOLKEYCTRL 0x38
00888 #define TVP3026_XCOLKEYCTRL_OVR_EN 0x01
00889 #define TVP3026_XCOLKEYCTRL_RED_EN 0x02
00890 #define TVP3026_XCOLKEYCTRL_GREEN_EN 0x04
00891 #define TVP3026_XCOLKEYCTRL_BLUE_EN 0x08
00892 #define TVP3026_XCOLKEYCTRL_NEGATE 0x10
00893 #define TVP3026_XCOLKEYCTRL_ZOOM1 0x00
00894 #define TVP3026_XCOLKEYCTRL_ZOOM2 0x20
00895 #define TVP3026_XCOLKEYCTRL_ZOOM4 0x40
00896 #define TVP3026_XCOLKEYCTRL_ZOOM8 0x60
00897 #define TVP3026_XCOLKEYCTRL_ZOOM16 0x80
00898 #define TVP3026_XCOLKEYCTRL_ZOOM32 0xA0
00899 #define TVP3026_XMEMPLLCTRL 0x39
00900 #define TVP3026_XMEMPLLCTRL_DIV(X) (((X)-1)>>1)
00901 #define TVP3026_XMEMPLLCTRL_STROBEMKC4 0x08
00902 #define TVP3026_XMEMPLLCTRL_MCLK_DOTCLOCK 0x00
00903 #define TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL 0x10
00904 #define TVP3026_XMEMPLLCTRL_RCLK_PIXPLL 0x00
00905 #define TVP3026_XMEMPLLCTRL_RCLK_LOOPPLL 0x20
00906 #define TVP3026_XMEMPLLCTRL_RCLK_DOTDIVN 0x40
00907 #define TVP3026_XSENSETEST 0x3A
00908 #define TVP3026_XTESTMODEDATA 0x3B
00909 #define TVP3026_XCRCREML 0x3C
00910 #define TVP3026_XCRCREMH 0x3D
00911 #define TVP3026_XCRCBITSEL 0x3E
00912 #define TVP3026_XID 0x3F
00913
00914 #endif
00915
00916 #ifdef NEED_DAC1064
00917
00918 #define DAC1064_OPT_SCLK_PCI 0x00
00919 #define DAC1064_OPT_SCLK_PLL 0x01
00920 #define DAC1064_OPT_SCLK_EXT 0x02
00921 #define DAC1064_OPT_SCLK_MASK 0x03
00922 #define DAC1064_OPT_GDIV1 0x04
00923 #define DAC1064_OPT_GDIV3 0x00
00924 #define DAC1064_OPT_MDIV1 0x08
00925 #define DAC1064_OPT_MDIV2 0x00
00926 #define DAC1064_OPT_RESERVED 0x10
00927
00928 #define M1064_INDEX 0x00
00929 #define M1064_PALWRADD 0x00
00930 #define M1064_PALDATA 0x01
00931 #define M1064_PIXRDMSK 0x02
00932 #define M1064_PALRDADD 0x03
00933 #define M1064_X_DATAREG 0x0A
00934 #define M1064_CURPOSXL 0x0C
00935 #define M1064_CURPOSXH 0x0D
00936 #define M1064_CURPOSYL 0x0E
00937 #define M1064_CURPOSYH 0x0F
00938
00939 #define M1064_XCURADDL 0x04
00940 #define M1064_XCURADDH 0x05
00941 #define M1064_XCURCTRL 0x06
00942 #define M1064_XCURCTRL_DIS 0x00
00943 #define M1064_XCURCTRL_3COLOR 0x01
00944 #define M1064_XCURCTRL_XGA 0x02
00945 #define M1064_XCURCTRL_XWIN 0x03
00946 #define M1064_XCURCOL0RED 0x08
00947 #define M1064_XCURCOL0GREEN 0x09
00948 #define M1064_XCURCOL0BLUE 0x0A
00949 #define M1064_XCURCOL1RED 0x0C
00950 #define M1064_XCURCOL1GREEN 0x0D
00951 #define M1064_XCURCOL1BLUE 0x0E
00952 #define M1064_XCURCOL2RED 0x10
00953 #define M1064_XCURCOL2GREEN 0x11
00954 #define M1064_XCURCOL2BLUE 0x12
00955 #define DAC1064_XVREFCTRL 0x18
00956 #define DAC1064_XVREFCTRL_INTERNAL 0x3F
00957 #define DAC1064_XVREFCTRL_EXTERNAL 0x00
00958 #define DAC1064_XVREFCTRL_G100_DEFAULT 0x03
00959 #define M1064_XMULCTRL 0x19
00960 #define M1064_XMULCTRL_DEPTH_8BPP 0x00
00961 #define M1064_XMULCTRL_DEPTH_15BPP_1BPP 0x01
00962 #define M1064_XMULCTRL_DEPTH_16BPP 0x02
00963 #define M1064_XMULCTRL_DEPTH_24BPP 0x03
00964 #define M1064_XMULCTRL_DEPTH_24BPP_8BPP 0x04
00965 #define M1064_XMULCTRL_2G8V16 0x05
00966 #define M1064_XMULCTRL_G16V16 0x06
00967 #define M1064_XMULCTRL_DEPTH_32BPP 0x07
00968 #define M1064_XMULCTRL_GRAPHICS_PALETIZED 0x00
00969 #define M1064_XMULCTRL_VIDEO_PALETIZED 0x08
00970 #define M1064_XPIXCLKCTRL 0x1A
00971 #define M1064_XPIXCLKCTRL_SRC_PCI 0x00
00972 #define M1064_XPIXCLKCTRL_SRC_PLL 0x01
00973 #define M1064_XPIXCLKCTRL_SRC_EXT 0x02
00974 #define M1064_XPIXCLKCTRL_SRC_MASK 0x03
00975 #define M1064_XPIXCLKCTRL_EN 0x00
00976 #define M1064_XPIXCLKCTRL_DIS 0x04
00977 #define M1064_XPIXCLKCTRL_PLL_DOWN 0x00
00978 #define M1064_XPIXCLKCTRL_PLL_UP 0x08
00979 #define M1064_XGENCTRL 0x1D
00980 #define M1064_XGENCTRL_VS_0 0x00
00981 #define M1064_XGENCTRL_VS_1 0x01
00982 #define M1064_XGENCTRL_ALPHA_DIS 0x00
00983 #define M1064_XGENCTRL_ALPHA_EN 0x02
00984 #define M1064_XGENCTRL_BLACK_0IRE 0x00
00985 #define M1064_XGENCTRL_BLACK_75IRE 0x10
00986 #define M1064_XGENCTRL_SYNC_ON_GREEN 0x00
00987 #define M1064_XGENCTRL_NO_SYNC_ON_GREEN 0x20
00988 #define M1064_XGENCTRL_SYNC_ON_GREEN_MASK 0x20
00989 #define M1064_XMISCCTRL 0x1E
00990 #define M1064_XMISCCTRL_DAC_DIS 0x00
00991 #define M1064_XMISCCTRL_DAC_EN 0x01
00992 #define M1064_XMISCCTRL_MFC_VGA 0x00
00993 #define M1064_XMISCCTRL_MFC_MAFC 0x02
00994 #define M1064_XMISCCTRL_MFC_DIS 0x06
00995 #define M1064_XMISCCTRL_DAC_6BIT 0x00
00996 #define M1064_XMISCCTRL_DAC_8BIT 0x08
00997 #define M1064_XMISCCTRL_LUT_DIS 0x00
00998 #define M1064_XMISCCTRL_LUT_EN 0x10
00999 #define M1064_XGENIOCTRL 0x2A
01000 #define M1064_XGENIODATA 0x2B
01001 #define DAC1064_XSYSPLLM 0x2C
01002 #define DAC1064_XSYSPLLN 0x2D
01003 #define DAC1064_XSYSPLLP 0x2E
01004 #define DAC1064_XSYSPLLSTAT 0x2F
01005 #define M1064_XZOOMCTRL 0x38
01006 #define M1064_XZOOMCTRL_1 0x00
01007 #define M1064_XZOOMCTRL_2 0x01
01008 #define M1064_XZOOMCTRL_4 0x03
01009 #define M1064_XSENSETEST 0x3A
01010 #define M1064_XSENSETEST_BCOMP 0x01
01011 #define M1064_XSENSETEST_GCOMP 0x02
01012 #define M1064_XSENSETEST_RCOMP 0x04
01013 #define M1064_XSENSETEST_PDOWN 0x00
01014 #define M1064_XSENSETEST_PUP 0x80
01015 #define M1064_XCRCREML 0x3C
01016 #define M1064_XCRCREMH 0x3D
01017 #define M1064_XCRCBITSEL 0x3E
01018 #define M1064_XCOLKEYMASKL 0x40
01019 #define M1064_XCOLKEYMASKH 0x41
01020 #define M1064_XCOLKEYL 0x42
01021 </