include/linux/pci.h

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/*
 *      $Id: pci.h,v 1.87 1998/10/11 15:13:12 mj Exp $
 *
 *      PCI defines and function prototypes
 *      Copyright 1994, Drew Eckhardt
 *      Copyright 1997--1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
 *
 *      For more information, please consult the following manuals (look at
 *      http://www.pcisig.com/ for how to get them):
 *
 *      PCI BIOS Specification
 *      PCI Local Bus Specification
 *      PCI to PCI Bridge Specification
 *      PCI System Design Guide
 */

#ifndef LINUX_PCI_H
#define LINUX_PCI_H

/*
 * Under PCI, each device has 256 bytes of configuration address space,
 * of which the first 64 bytes are standardized as follows:
 */
#define PCI_VENDOR_ID           0x00    /* 16 bits */
#define PCI_DEVICE_ID           0x02    /* 16 bits */
#define PCI_COMMAND             0x04    /* 16 bits */
#define  PCI_COMMAND_IO         0x1     /* Enable response in I/O space */
#define  PCI_COMMAND_MEMORY     0x2     /* Enable response in Memory space */
#define  PCI_COMMAND_MASTER     0x4     /* Enable bus mastering */
#define  PCI_COMMAND_SPECIAL    0x8     /* Enable response to special cycles */
#define  PCI_COMMAND_INVALIDATE 0x10    /* Use memory write and invalidate */
#define  PCI_COMMAND_VGA_PALETTE 0x20   /* Enable palette snooping */
#define  PCI_COMMAND_PARITY     0x40    /* Enable parity checking */
#define  PCI_COMMAND_WAIT       0x80    /* Enable address/data stepping */
#define  PCI_COMMAND_SERR       0x100   /* Enable SERR */
#define  PCI_COMMAND_FAST_BACK  0x200   /* Enable back-to-back writes */

#define PCI_STATUS              0x06    /* 16 bits */
#define  PCI_STATUS_CAP_LIST    0x10    /* Support Capability List */
#define  PCI_STATUS_66MHZ       0x20    /* Support 66 Mhz PCI 2.1 bus */
#define  PCI_STATUS_UDF         0x40    /* Support User Definable Features */
#define  PCI_STATUS_FAST_BACK   0x80    /* Accept fast-back to back */
#define  PCI_STATUS_PARITY      0x100   /* Detected parity error */
#define  PCI_STATUS_DEVSEL_MASK 0x600   /* DEVSEL timing */
#define  PCI_STATUS_DEVSEL_FAST 0x000   
#define  PCI_STATUS_DEVSEL_MEDIUM 0x200
#define  PCI_STATUS_DEVSEL_SLOW 0x400
#define  PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
#define  PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
#define  PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
#define  PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
#define  PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */

#define PCI_CLASS_REVISION      0x08    /* High 24 bits are class, low 8
                                           revision */
#define PCI_REVISION_ID         0x08    /* Revision ID */
#define PCI_CLASS_PROG          0x09    /* Reg. Level Programming Interface */
#define PCI_CLASS_DEVICE        0x0a    /* Device class */

#define PCI_CACHE_LINE_SIZE     0x0c    /* 8 bits */
#define PCI_LATENCY_TIMER       0x0d    /* 8 bits */
#define PCI_HEADER_TYPE         0x0e    /* 8 bits */
#define  PCI_HEADER_TYPE_NORMAL 0
#define  PCI_HEADER_TYPE_BRIDGE 1
#define  PCI_HEADER_TYPE_CARDBUS 2

#define PCI_BIST                0x0f    /* 8 bits */
#define PCI_BIST_CODE_MASK      0x0f    /* Return result */
#define PCI_BIST_START          0x40    /* 1 to start BIST, 2 secs or less */
#define PCI_BIST_CAPABLE        0x80    /* 1 if BIST capable */

/*
 * Base addresses specify locations in memory or I/O space.
 * Decoded size can be determined by writing a value of 
 * 0xffffffff to the register, and reading it back.  Only 
 * 1 bits are decoded.
 */
#define PCI_BASE_ADDRESS_0      0x10    /* 32 bits */
#define PCI_BASE_ADDRESS_1      0x14    /* 32 bits [htype 0,1 only] */
#define PCI_BASE_ADDRESS_2      0x18    /* 32 bits [htype 0 only] */
#define PCI_BASE_ADDRESS_3      0x1c    /* 32 bits */
#define PCI_BASE_ADDRESS_4      0x20    /* 32 bits */
#define PCI_BASE_ADDRESS_5      0x24    /* 32 bits */
#define  PCI_BASE_ADDRESS_SPACE 0x01    /* 0 = memory, 1 = I/O */
#define  PCI_BASE_ADDRESS_SPACE_IO 0x01
#define  PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
#define  PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
#define  PCI_BASE_ADDRESS_MEM_TYPE_32   0x00    /* 32 bit address */
#define  PCI_BASE_ADDRESS_MEM_TYPE_1M   0x02    /* Below 1M */
#define  PCI_BASE_ADDRESS_MEM_TYPE_64   0x04    /* 64 bit address */
#define  PCI_BASE_ADDRESS_MEM_PREFETCH  0x08    /* prefetchable? */
#define  PCI_BASE_ADDRESS_MEM_MASK      (~0x0fUL)
#define  PCI_BASE_ADDRESS_IO_MASK       (~0x03UL)
/* bit 1 is reserved if address_space = 1 */

/* Header type 0 (normal devices) */
#define PCI_CARDBUS_CIS         0x28
#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
#define PCI_SUBSYSTEM_ID        0x2e  
#define PCI_ROM_ADDRESS         0x30    /* Bits 31..11 are address, 10..1 reserved */
#define  PCI_ROM_ADDRESS_ENABLE 0x01
#define PCI_ROM_ADDRESS_MASK    (~0x7ffUL)

#define PCI_CAPABILITY_LIST     0x34    /* Offset of first capability list entry */

/* 0x35-0x3b are reserved */
#define PCI_INTERRUPT_LINE      0x3c    /* 8 bits */
#define PCI_INTERRUPT_PIN       0x3d    /* 8 bits */
#define PCI_MIN_GNT             0x3e    /* 8 bits */
#define PCI_MAX_LAT             0x3f    /* 8 bits */

/* Header type 1 (PCI-to-PCI bridges) */
#define PCI_PRIMARY_BUS         0x18    /* Primary bus number */
#define PCI_SECONDARY_BUS       0x19    /* Secondary bus number */
#define PCI_SUBORDINATE_BUS     0x1a    /* Highest bus number behind the bridge */
#define PCI_SEC_LATENCY_TIMER   0x1b    /* Latency timer for secondary interface */
#define PCI_IO_BASE             0x1c    /* I/O range behind the bridge */
#define PCI_IO_LIMIT            0x1d
#define  PCI_IO_RANGE_TYPE_MASK 0x0f    /* I/O bridging type */
#define  PCI_IO_RANGE_TYPE_16   0x00
#define  PCI_IO_RANGE_TYPE_32   0x01
#define  PCI_IO_RANGE_MASK      ~0x0f
#define PCI_SEC_STATUS          0x1e    /* Secondary status register, only bit 14 used */
#define PCI_MEMORY_BASE         0x20    /* Memory range behind */
#define PCI_MEMORY_LIMIT        0x22
#define  PCI_MEMORY_RANGE_TYPE_MASK 0x0f
#define  PCI_MEMORY_RANGE_MASK  ~0x0f
#define PCI_PREF_MEMORY_BASE    0x24    /* Prefetchable memory range behind */
#define PCI_PREF_MEMORY_LIMIT   0x26
#define  PCI_PREF_RANGE_TYPE_MASK 0x0f
#define  PCI_PREF_RANGE_TYPE_32 0x00
#define  PCI_PREF_RANGE_TYPE_64 0x01
#define  PCI_PREF_RANGE_MASK    ~0x0f
#define PCI_PREF_BASE_UPPER32   0x28    /* Upper half of prefetchable memory range */
#define PCI_PREF_LIMIT_UPPER32  0x2c
#define PCI_IO_BASE_UPPER16     0x30    /* Upper half of I/O addresses */
#define PCI_IO_LIMIT_UPPER16    0x32
/* 0x34-0x3b is reserved */
#define PCI_ROM_ADDRESS1        0x38    /* Same as PCI_ROM_ADDRESS, but for htype 1 */
/* 0x3c-0x3d are same as for htype 0 */
#define PCI_BRIDGE_CONTROL      0x3e
#define  PCI_BRIDGE_CTL_PARITY  0x01    /* Enable parity detection on secondary interface */
#define  PCI_BRIDGE_CTL_SERR    0x02    /* The same for SERR forwarding */
#define  PCI_BRIDGE_CTL_NO_ISA  0x04    /* Disable bridging of ISA ports */
#define  PCI_BRIDGE_CTL_VGA     0x08    /* Forward VGA addresses */
#define  PCI_BRIDGE_CTL_MASTER_ABORT 0x20  /* Report master aborts */
#define  PCI_BRIDGE_CTL_BUS_RESET 0x40  /* Secondary bus reset */
#define  PCI_BRIDGE_CTL_FAST_BACK 0x80  /* Fast Back2Back enabled on secondary interface */

/* Header type 2 (CardBus bridges) */
/* 0x14-0x15 reserved */
#define PCI_CB_SEC_STATUS       0x16    /* Secondary status */
#define PCI_CB_PRIMARY_BUS      0x18    /* PCI bus number */
#define PCI_CB_CARD_BUS         0x19    /* CardBus bus number */
#define PCI_CB_SUBORDINATE_BUS  0x1a    /* Subordinate bus number */
#define PCI_CB_LATENCY_TIMER    0x1b    /* CardBus latency timer */
#define PCI_CB_MEMORY_BASE_0    0x1c
#define PCI_CB_MEMORY_LIMIT_0   0x20
#define PCI_CB_MEMORY_BASE_1    0x24
#define PCI_CB_MEMORY_LIMIT_1   0x28
#define PCI_CB_IO_BASE_0        0x2c
#define PCI_CB_IO_BASE_0_HI     0x2e
#define PCI_CB_IO_LIMIT_0       0x30
#define PCI_CB_IO_LIMIT_0_HI    0x32
#define PCI_CB_IO_BASE_1        0x34
#define PCI_CB_IO_BASE_1_HI     0x36
#define PCI_CB_IO_LIMIT_1       0x38
#define PCI_CB_IO_LIMIT_1_HI    0x3a
#define  PCI_CB_IO_RANGE_MASK   ~0x03
/* 0x3c-0x3d are same as for htype 0 */
#define PCI_CB_BRIDGE_CONTROL   0x3e
#define  PCI_CB_BRIDGE_CTL_PARITY       0x01    /* Similar to standard bridge control register */
#define  PCI_CB_BRIDGE_CTL_SERR         0x02
#define  PCI_CB_BRIDGE_CTL_ISA          0x04
#define  PCI_CB_BRIDGE_CTL_VGA          0x08
#define  PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
#define  PCI_CB_BRIDGE_CTL_CB_RESET     0x40    /* CardBus reset */
#define  PCI_CB_BRIDGE_CTL_16BIT_INT    0x80    /* Enable interrupt for 16-bit cards */
#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100  /* Prefetch enable for both memory regions */
#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
#define  PCI_CB_BRIDGE_CTL_POST_WRITES  0x400
#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
#define PCI_CB_SUBSYSTEM_ID     0x42
#define PCI_CB_LEGACY_MODE_BASE 0x44    /* 16-bit PC Card legacy mode base address (ExCa) */
/* 0x48-0x7f reserved */

/* Capability lists */
#define PCI_CAP_LIST_ID         0       /* Capability ID */
#define  PCI_CAP_ID_PM          0x01    /* Power Management */
#define  PCI_CAP_ID_AGP         0x02    /* Accelerated Graphics Port */
#define PCI_CAP_LIST_NEXT       1       /* Next capability in the list */

/* Power Management Registers */

#define  PCI_PM_CAP_VER_MASK    0x0007  /* Version */
#define  PCI_PM_CAP_PME_CLOCK   0x0008  /* PME clock required */
#define  PCI_PM_CAP_AUX_POWER   0x0010  /* Auxilliary power support */
#define  PCI_PM_CAP_DSI         0x0020  /* Device specific initialization */
#define  PCI_PM_CAP_D1          0x0200  /* D1 power state support */
#define  PCI_PM_CAP_D2          0x0400  /* D2 power state support */
#define  PCI_PM_CAP_PME         0x0800  /* PME pin supported */
#define PCI_PM_CTRL             4       /* PM control and status register */
#define  PCI_PM_CTRL_STATE_MASK 0x0003  /* Current power state (D0 to D3) */
#define  PCI_PM_CTRL_PME_ENABLE 0x0100  /* PME pin enable */
#define  PCI_PM_CTRL_DATA_SEL_MASK      0x1e00  /* Data select (??) */
#define  PCI_PM_CTRL_DATA_SCALE_MASK    0x6000  /* Data scale (??) */
#define  PCI_PM_CTRL_PME_STATUS 0x8000  /* PME pin status */
#define PCI_PM_PPB_EXTENSIONS   6       /* PPB support extensions (??) */
#define  PCI_PM_PPB_B2_B3       0x40    /* Stop clock when in D3hot (??) */
#define  PCI_PM_BPCC_ENABLE     0x80    /* Bus power/clock control enable (??) */
#define PCI_PM_DATA_REGISTER    7       /* (??) */
#define PCI_PM_SIZEOF           8

/* Device classes and subclasses */

#define PCI_CLASS_NOT_DEFINED           0x0000
#define PCI_CLASS_NOT_DEFINED_VGA       0x0001

#define PCI_BASE_CLASS_STORAGE          0x01
#define PCI_CLASS_STORAGE_SCSI          0x0100
#define PCI_CLASS_STORAGE_IDE           0x0101
#define PCI_CLASS_STORAGE_FLOPPY        0x0102
#define PCI_CLASS_STORAGE_IPI           0x0103
#define PCI_CLASS_STORAGE_RAID          0x0104
#define PCI_CLASS_STORAGE_OTHER         0x0180

#define PCI_BASE_CLASS_NETWORK          0x02
#define PCI_CLASS_NETWORK_ETHERNET      0x0200
#define PCI_CLASS_NETWORK_TOKEN_RING    0x0201
#define PCI_CLASS_NETWORK_FDDI          0x0202
#define PCI_CLASS_NETWORK_ATM           0x0203
#define PCI_CLASS_NETWORK_OTHER         0x0280

#define PCI_BASE_CLASS_DISPLAY          0x03
#define PCI_CLASS_DISPLAY_VGA           0x0300
#define PCI_CLASS_DISPLAY_XGA           0x0301
#define PCI_CLASS_DISPLAY_OTHER         0x0380

#define PCI_BASE_CLASS_MULTIMEDIA       0x04
#define PCI_CLASS_MULTIMEDIA_VIDEO      0x0400
#define PCI_CLASS_MULTIMEDIA_AUDIO      0x0401
#define PCI_CLASS_MULTIMEDIA_OTHER      0x0480

#define PCI_BASE_CLASS_MEMORY           0x05
#define  PCI_CLASS_MEMORY_RAM           0x0500
#define  PCI_CLASS_MEMORY_FLASH         0x0501
#define  PCI_CLASS_MEMORY_OTHER         0x0580

#define PCI_BASE_CLASS_BRIDGE           0x06
#define  PCI_CLASS_BRIDGE_HOST          0x0600
#define  PCI_CLASS_BRIDGE_ISA           0x0601
#define  PCI_CLASS_BRIDGE_EISA          0x0602
#define  PCI_CLASS_BRIDGE_MC            0x0603
#define  PCI_CLASS_BRIDGE_PCI           0x0604
#define  PCI_CLASS_BRIDGE_PCMCIA        0x0605
#define  PCI_CLASS_BRIDGE_NUBUS         0x0606
#define  PCI_CLASS_BRIDGE_CARDBUS       0x0607
#define  PCI_CLASS_BRIDGE_OTHER         0x0680

#define PCI_BASE_CLASS_COMMUNICATION    0x07
#define PCI_CLASS_COMMUNICATION_SERIAL  0x0700
#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701
#define PCI_CLASS_COMMUNICATION_OTHER   0x0780

#define PCI_BASE_CLASS_SYSTEM           0x08
#define PCI_CLASS_SYSTEM_PIC            0x0800
#define PCI_CLASS_SYSTEM_DMA            0x0801
#define PCI_CLASS_SYSTEM_TIMER          0x0802
#define PCI_CLASS_SYSTEM_RTC            0x0803
#define PCI_CLASS_SYSTEM_OTHER          0x0880

#define PCI_BASE_CLASS_INPUT            0x09
#define PCI_CLASS_INPUT_KEYBOARD        0x0900
#define PCI_CLASS_INPUT_PEN             0x0901
#define PCI_CLASS_INPUT_MOUSE           0x0902
#define PCI_CLASS_INPUT_OTHER           0x0980

#define PCI_BASE_CLASS_DOCKING          0x0a
#define PCI_CLASS_DOCKING_GENERIC       0x0a00
#define PCI_CLASS_DOCKING_OTHER         0x0a01

#define PCI_BASE_CLASS_PROCESSOR        0x0b
#define PCI_CLASS_PROCESSOR_386         0x0b00
#define PCI_CLASS_PROCESSOR_486         0x0b01
#define PCI_CLASS_PROCESSOR_PENTIUM     0x0b02
#define PCI_CLASS_PROCESSOR_ALPHA       0x0b10
#define PCI_CLASS_PROCESSOR_POWERPC     0x0b20
#define PCI_CLASS_PROCESSOR_CO          0x0b40

#define PCI_BASE_CLASS_SERIAL           0x0c
#define PCI_CLASS_SERIAL_FIREWIRE       0x0c00
#define PCI_CLASS_SERIAL_ACCESS         0x0c01
#define PCI_CLASS_SERIAL_SSA            0x0c02
#define PCI_CLASS_SERIAL_USB            0x0c03
#define PCI_CLASS_SERIAL_FIBER          0x0c04
#define PCI_CLASS_SERIAL_SMBUS          0x0c05

#define PCI_BASE_CLASS_INTELLIGENT      0x0e
#define PCI_CLASS_INTELLIGENT_I2O       0x0e00

#define PCI_CLASS_HOT_SWAP_CONTROLLER   0xff00

#define PCI_CLASS_OTHERS                0xff

/*
 * Vendor and card ID's: sort these numerically according to vendor
 * (and according to card ID within vendor). Send all updates to
 * <linux-pcisupport@cck.uni-kl.de>.
 */
#define PCI_VENDOR_ID_DYNALINK          0x0675
#define PCI_DEVICE_ID_DYNALINK_IS64PH   0x1702

#define PCI_VENDOR_ID_BERKOM                    0x0871
#define PCI_DEVICE_ID_BERKOM_A1T                0xFFA1
#define PCI_DEVICE_ID_BERKOM_T_CONCEPT          0xFFA2
#define PCI_DEVICE_ID_BERKOM_A4T                0xFFA4
#define PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO      0xFFA8

#define PCI_VENDOR_ID_COMPAQ            0x0e11
#define PCI_DEVICE_ID_COMPAQ_TOKENRING  0x0508
#define PCI_DEVICE_ID_COMPAQ_1280       0x3033
#define PCI_DEVICE_ID_COMPAQ_TRIFLEX    0x4000
#define PCI_DEVICE_ID_COMPAQ_6010       0x6010
#define PCI_DEVICE_ID_COMPAQ_SMART2P    0xae10
#define PCI_DEVICE_ID_COMPAQ_NETEL100   0xae32
#define PCI_DEVICE_ID_COMPAQ_NETEL10    0xae34
#define PCI_DEVICE_ID_COMPAQ_NETFLEX3I  0xae35
#define PCI_DEVICE_ID_COMPAQ_NETEL100D  0xae40
#define PCI_DEVICE_ID_COMPAQ_NETEL100PI 0xae43
#define PCI_DEVICE_ID_COMPAQ_NETEL100I  0xb011
#define PCI_DEVICE_ID_COMPAQ_CISS       0xb060
#define PCI_DEVICE_ID_COMPAQ_CISSB      0xb178
#define PCI_DEVICE_ID_COMPAQ_THUNDER    0xf130
#define PCI_DEVICE_ID_COMPAQ_NETFLEX3B  0xf150

#define PCI_VENDOR_ID_NCR               0x1000
#define PCI_DEVICE_ID_NCR_53C810        0x0001
#define PCI_DEVICE_ID_NCR_53C820        0x0002
#define PCI_DEVICE_ID_NCR_53C825        0x0003
#define PCI_DEVICE_ID_NCR_53C815        0x0004
#define PCI_DEVICE_ID_NCR_53C860        0x0006
#define PCI_DEVICE_ID_NCR_53C1510D      0x000a
#define PCI_DEVICE_ID_NCR_53C896        0x000b
#define PCI_DEVICE_ID_NCR_53C895        0x000c
#define PCI_DEVICE_ID_NCR_53C885        0x000d
#define PCI_DEVICE_ID_NCR_53C875        0x000f
#define PCI_DEVICE_ID_NCR_53C1510       0x0010
#define PCI_DEVICE_ID_NCR_53C875J       0x008f

#define PCI_VENDOR_ID_ATI               0x1002
#define PCI_DEVICE_ID_ATI_68800         0x4158
#define PCI_DEVICE_ID_ATI_215CT222      0x4354
#define PCI_DEVICE_ID_ATI_210888CX      0x4358
#define PCI_DEVICE_ID_ATI_215GB         0x4742
#define PCI_DEVICE_ID_ATI_215GD         0x4744
#define PCI_DEVICE_ID_ATI_215GI         0x4749
#define PCI_DEVICE_ID_ATI_215GP         0x4750
#define PCI_DEVICE_ID_ATI_215GQ         0x4751
#define PCI_DEVICE_ID_ATI_215GT         0x4754
#define PCI_DEVICE_ID_ATI_215GTB        0x4755
#define PCI_DEVICE_ID_ATI_210888GX      0x4758
#define PCI_DEVICE_ID_ATI_RAGE128_LE    0x4c45
#define PCI_DEVICE_ID_ATI_RAGE128_LF    0x4c46
#define PCI_DEVICE_ID_ATI_215LG         0x4c47
#define PCI_DEVICE_ID_ATI_264LT         0x4c54
#define PCI_DEVICE_ID_ATI_RAGE128_PF    0x5046
#define PCI_DEVICE_ID_ATI_RAGE128_PR    0x5052
#define PCI_DEVICE_ID_ATI_RAGE128_RE    0x5245
#define PCI_DEVICE_ID_ATI_RAGE128_RF    0x5246
#define PCI_DEVICE_ID_ATI_RAGE128_RK    0x524b
#define PCI_DEVICE_ID_ATI_RAGE128_RL    0x524c
#define PCI_DEVICE_ID_ATI_264VT         0x5654

#define PCI_VENDOR_ID_VLSI              0x1004
#define PCI_DEVICE_ID_VLSI_82C592       0x0005
#define PCI_DEVICE_ID_VLSI_82C593       0x0006
#define PCI_DEVICE_ID_VLSI_82C594       0x0007
#define PCI_DEVICE_ID_VLSI_82C597       0x0009
#define PCI_DEVICE_ID_VLSI_82C541       0x000c
#define PCI_DEVICE_ID_VLSI_82C543       0x000d
#define PCI_DEVICE_ID_VLSI_82C532       0x0101
#define PCI_DEVICE_ID_VLSI_82C534       0x0102
#define PCI_DEVICE_ID_VLSI_82C535       0x0104
#define PCI_DEVICE_ID_VLSI_82C147       0x0105
#define PCI_DEVICE_ID_VLSI_VAS96011     0x0702

#define PCI_VENDOR_ID_ADL               0x1005
#define PCI_DEVICE_ID_ADL_2301          0x2301

#define PCI_VENDOR_ID_NS                0x100b
#define PCI_DEVICE_ID_NS_87415          0x0002
#define PCI_DEVICE_ID_NS_87410          0xd001

#define PCI_VENDOR_ID_TSENG             0x100c
#define PCI_DEVICE_ID_TSENG_W32P_2      0x3202
#define PCI_DEVICE_ID_TSENG_W32P_b      0x3205
#define PCI_DEVICE_ID_TSENG_W32P_c      0x3206
#define PCI_DEVICE_ID_TSENG_W32P_d      0x3207
#define PCI_DEVICE_ID_TSENG_ET6000      0x3208

#define PCI_VENDOR_ID_WEITEK            0x100e
#define PCI_DEVICE_ID_WEITEK_P9000      0x9001
#define PCI_DEVICE_ID_WEITEK_P9100      0x9100

#define PCI_VENDOR_ID_DEC               0x1011
#define PCI_DEVICE_ID_DEC_BRD           0x0001
#define PCI_DEVICE_ID_DEC_TULIP         0x0002
#define PCI_DEVICE_ID_DEC_TGA           0x0004
#define PCI_DEVICE_ID_DEC_TULIP_FAST    0x0009
#define PCI_DEVICE_ID_DEC_TGA2          0x000D
#define PCI_DEVICE_ID_DEC_FDDI          0x000F
#define PCI_DEVICE_ID_DEC_TULIP_PLUS    0x0014
#define PCI_DEVICE_ID_DEC_21142         0x0019
#define PCI_DEVICE_ID_DEC_21052         0x0021
#define PCI_DEVICE_ID_DEC_21150         0x0022
#define PCI_DEVICE_ID_DEC_21152         0x0024
#define PCI_DEVICE_ID_DEC_21153         0x0025
#define PCI_DEVICE_ID_DEC_21154         0x0026
#define PCI_DEVICE_ID_DEC_21285         0x1065
#define PCI_DEVICE_ID_DEC_21554         0x0046
#define PCI_DEVICE_ID_COMPAQ_42XX       0x0046

#define PCI_VENDOR_ID_CIRRUS            0x1013
#define PCI_DEVICE_ID_CIRRUS_7548       0x0038
#define PCI_DEVICE_ID_CIRRUS_5430       0x00a0
#define PCI_DEVICE_ID_CIRRUS_5434_4     0x00a4
#define PCI_DEVICE_ID_CIRRUS_5434_8     0x00a8
#define PCI_DEVICE_ID_CIRRUS_5436       0x00ac
#define PCI_DEVICE_ID_CIRRUS_5446       0x00b8
#define PCI_DEVICE_ID_CIRRUS_5480       0x00bc
#define PCI_DEVICE_ID_CIRRUS_5464       0x00d4
#define PCI_DEVICE_ID_CIRRUS_5465       0x00d6
#define PCI_DEVICE_ID_CIRRUS_6729       0x1100
#define PCI_DEVICE_ID_CIRRUS_6832       0x1110
#define PCI_DEVICE_ID_CIRRUS_7542       0x1200
#define PCI_DEVICE_ID_CIRRUS_7543       0x1202
#define PCI_DEVICE_ID_CIRRUS_7541       0x1204

#define PCI_VENDOR_ID_IBM               0x1014
#define PCI_DEVICE_ID_IBM_FIRE_CORAL    0x000a
#define PCI_DEVICE_ID_IBM_TR            0x0018
#define PCI_DEVICE_ID_IBM_82G2675       0x001d
#define PCI_DEVICE_ID_IBM_MCA           0x0020
#define PCI_DEVICE_ID_IBM_82351         0x0022
#define PCI_DEVICE_ID_IBM_PYTHON        0x002d
#define PCI_DEVICE_ID_IBM_SERVERAID     0x002e
#define PCI_DEVICE_ID_IBM_TR_WAKE       0x003e
#define PCI_DEVICE_ID_IBM_MPIC          0x0046
#define PCI_DEVICE_ID_IBM_3780IDSP      0x007d
#define PCI_DEVICE_ID_IBM_SERVERAIDI960 0x01bd
#define PCI_DEVICE_ID_IBM_MPIC_2        0xffff

#define PCI_VENDOR_ID_WD                0x101c
#define PCI_DEVICE_ID_WD_7197           0x3296

#define PCI_VENDOR_ID_AMD               0x1022
#define PCI_DEVICE_ID_AMD_LANCE         0x2000
#define PCI_DEVICE_ID_AMD_LANCE_HOME    0x2001
#define PCI_DEVICE_ID_AMD_SCSI          0x2020

#define PCI_VENDOR_ID_TRIDENT           0x1023
#define PCI_DEVICE_ID_TRIDENT_9397      0x9397
#define PCI_DEVICE_ID_TRIDENT_9420      0x9420
#define PCI_DEVICE_ID_TRIDENT_9440      0x9440
#define PCI_DEVICE_ID_TRIDENT_9660      0x9660
#define PCI_DEVICE_ID_TRIDENT_9750      0x9750

#define PCI_VENDOR_ID_AI                0x1025
#define PCI_DEVICE_ID_AI_M1435          0x1435

#define PCI_VENDOR_ID_MATROX            0x102B
#define PCI_DEVICE_ID_MATROX_MGA_2      0x0518
#define PCI_DEVICE_ID_MATROX_MIL        0x0519
#define PCI_DEVICE_ID_MATROX_MYS        0x051A
#define PCI_DEVICE_ID_MATROX_MIL_2      0x051b
#define PCI_DEVICE_ID_MATROX_MIL_2_AGP  0x051f
#define PCI_DEVICE_ID_MATROX_G200_PCI   0x0520
#define PCI_DEVICE_ID_MATROX_G200_AGP   0x0521
#define PCI_DEVICE_ID_MATROX_MGA_IMP    0x0d10
#define PCI_DEVICE_ID_MATROX_G100_MM    0x1000
#define PCI_DEVICE_ID_MATROX_G100_AGP   0x1001

#define PCI_VENDOR_ID_CT                0x102c
#define PCI_DEVICE_ID_CT_65545          0x00d8
#define PCI_DEVICE_ID_CT_65548          0x00dc
#define PCI_DEVICE_ID_CT_65550          0x00e0
#define PCI_DEVICE_ID_CT_65554          0x00e4
#define PCI_DEVICE_ID_CT_65555          0x00e5

#define PCI_DEVICE_ID_PLX_R685          0x1030
#define PCI_DEVICE_ID_PLX_DJINN_ITOO    0x1151
#define PCI_DEVICE_ID_PLX_R753          0x1152

#define PCI_VENDOR_ID_MIRO              0x1031
#define PCI_DEVICE_ID_MIRO_36050        0x5601

#define PCI_VENDOR_ID_NEC               0x1033
#define PCI_DEVICE_ID_NEC_PCX2          0x0046

#define PCI_VENDOR_ID_FD                0x1036
#define PCI_DEVICE_ID_FD_36C70          0x0000

#define PCI_VENDOR_ID_SI                0x1039
#define PCI_DEVICE_ID_SI_5591_AGP       0x0001
#define PCI_DEVICE_ID_SI_6202           0x0002
#define PCI_DEVICE_ID_SI_503            0x0008
#define PCI_DEVICE_ID_SI_ACPI           0x0009
#define PCI_DEVICE_ID_SI_5597_VGA       0x0200
#define PCI_DEVICE_ID_SI_6205           0x0205
#define PCI_DEVICE_ID_SI_501            0x0406
#define PCI_DEVICE_ID_SI_496            0x0496
#define PCI_DEVICE_ID_SI_601            0x0601
#define PCI_DEVICE_ID_SI_5107           0x5107
#define PCI_DEVICE_ID_SI_5511           0x5511
#define PCI_DEVICE_ID_SI_5513           0x5513
#define PCI_DEVICE_ID_SI_5571           0x5571
#define PCI_DEVICE_ID_SI_5591           0x5591
#define PCI_DEVICE_ID_SI_5597           0x5597
#define PCI_DEVICE_ID_SI_7001           0x7001

#define PCI_VENDOR_ID_HP                0x103c
#define PCI_DEVICE_ID_HP_J2585A         0x1030
#define PCI_DEVICE_ID_HP_J2585B         0x1031

#define PCI_VENDOR_ID_PCTECH            0x1042
#define PCI_DEVICE_ID_PCTECH_RZ1000     0x1000
#define PCI_DEVICE_ID_PCTECH_RZ1001     0x1001
#define PCI_DEVICE_ID_PCTECH_SAMURAI_0  0x3000
#define PCI_DEVICE_ID_PCTECH_SAMURAI_1  0x3010
#define PCI_DEVICE_ID_PCTECH_SAMURAI_IDE 0x3020

#define PCI_VENDOR_ID_ASUSTEK           0x1043
#define PCI_DEVICE_ID_ASUSTEK_0675      0x0675

#define PCI_VENDOR_ID_DPT               0x1044   
#define PCI_DEVICE_ID_DPT               0xa400  

#define PCI_VENDOR_ID_OPTI              0x1045
#define PCI_DEVICE_ID_OPTI_92C178       0xc178
#define PCI_DEVICE_ID_OPTI_82C557       0xc557
#define PCI_DEVICE_ID_OPTI_82C558       0xc558
#define PCI_DEVICE_ID_OPTI_82C621       0xc621
#define PCI_DEVICE_ID_OPTI_82C700       0xc700
#define PCI_DEVICE_ID_OPTI_82C701       0xc701
#define PCI_DEVICE_ID_OPTI_82C814       0xc814
#define PCI_DEVICE_ID_OPTI_82C822       0xc822
#define PCI_DEVICE_ID_OPTI_82C861       0xc861
#define PCI_DEVICE_ID_OPTI_82C825       0xd568

#define PCI_VENDOR_ID_ELSA              0x1048
#define PCI_DEVICE_ID_ELSA_MICROLINK    0x1000
#define PCI_DEVICE_ID_ELSA_QS3000       0x3000

#define PCI_VENDOR_ID_SGS               0x104a
#define PCI_DEVICE_ID_SGS_2000          0x0008
#define PCI_DEVICE_ID_SGS_1764          0x0009

#define PCI_VENDOR_ID_BUSLOGIC                0x104B
#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC 0x0140
#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER    0x1040
#define PCI_DEVICE_ID_BUSLOGIC_FLASHPOINT     0x8130

#define PCI_VENDOR_ID_TI                0x104c
#define PCI_DEVICE_ID_TI_TVP4010        0x3d04
#define PCI_DEVICE_ID_TI_TVP4020        0x3d07
#define PCI_DEVICE_ID_TI_PCI1130        0xac12
#define PCI_DEVICE_ID_TI_PCI1031        0xac13
#define PCI_DEVICE_ID_TI_PCI1131        0xac15
#define PCI_DEVICE_ID_TI_PCI1250        0xac16
#define PCI_DEVICE_ID_TI_PCI1220        0xac17

#define PCI_VENDOR_ID_OAK               0x104e
#define PCI_DEVICE_ID_OAK_OTI107        0x0107

/* Winbond have two vendor IDs! See 0x10ad as well */
#define PCI_VENDOR_ID_WINBOND2          0x1050
#define PCI_DEVICE_ID_WINBOND2_89C940   0x0940
#define PCI_DEVICE_ID_WINBOND2_6692     0x6692

#define PCI_VENDOR_ID_ANIGMA            0x1051
#define PCI_DEVICE_ID_ANIGMA_MC145575   0x0100

#define PCI_VENDOR_ID_MOTOROLA          0x1057
#define PCI_VENDOR_ID_MOTOROLA_OOPS     0x1507
#define PCI_DEVICE_ID_MOTOROLA_MPC105   0x0001
#define PCI_DEVICE_ID_MOTOROLA_MPC106   0x0002
#define PCI_DEVICE_ID_MOTOROLA_RAVEN    0x4801
#define PCI_DEVICE_ID_MOTOROLA_FALCON   0x4802
#define PCI_DEVICE_ID_MOTOROLA_CPX8216  0x4806

#define PCI_VENDOR_ID_PROMISE           0x105a
#define PCI_DEVICE_ID_PROMISE_20246     0x4d33
#define PCI_DEVICE_ID_PROMISE_5300      0x5300

#define PCI_VENDOR_ID_N9                0x105d
#define PCI_DEVICE_ID_N9_I128           0x2309
#define PCI_DEVICE_ID_N9_I128_2         0x2339
#define PCI_DEVICE_ID_N9_I128_T2R       0x493d

#define PCI_VENDOR_ID_UMC               0x1060
#define PCI_DEVICE_ID_UMC_UM8673F       0x0101
#define PCI_DEVICE_ID_UMC_UM8891A       0x0891
#define PCI_DEVICE_ID_UMC_UM8886BF      0x673a
#define PCI_DEVICE_ID_UMC_UM8886A       0x886a
#define PCI_DEVICE_ID_UMC_UM8881F       0x8881
#define PCI_DEVICE_ID_UMC_UM8886F       0x8886
#define PCI_DEVICE_ID_UMC_UM9017F       0x9017
#define PCI_DEVICE_ID_UMC_UM8886N       0xe886
#define PCI_DEVICE_ID_UMC_UM8891N       0xe891

#define PCI_VENDOR_ID_X                 0x1061
#define PCI_DEVICE_ID_X_AGX016          0x0001

#define PCI_VENDOR_ID_PICOP             0x1066
#define PCI_DEVICE_ID_PICOP_PT86C52X    0x0001
#define PCI_DEVICE_ID_PICOP_PT80C524    0x8002

#define PCI_VENDOR_ID_MYLEX             0x1069
#define PCI_DEVICE_ID_MYLEX_DAC960_P    0x0001
#define PCI_DEVICE_ID_MYLEX_DAC960_PD   0x0002
#define PCI_DEVICE_ID_MYLEX_DAC960_PG   0x0010
#define PCI_DEVICE_ID_MYLEX_DAC960_LA   0x0020
#define PCI_DEVICE_ID_MYLEX_DAC960_LP   0x0050
#define PCI_DEVICE_ID_MYLEX_DAC960_BA   0xBA56

#define PCI_VENDOR_ID_APPLE             0x106b
#define PCI_DEVICE_ID_APPLE_BANDIT      0x0001
#define PCI_DEVICE_ID_APPLE_GC          0x0002
#define PCI_DEVICE_ID_APPLE_HYDRA       0x000e
#define PCI_DEVICE_ID_APPLE_UNI_N_FW    0x0018
#define PCI_DEVICE_ID_APPLE_KL_USB      0x0019
#define PCI_DEVICE_ID_APPLE_UNI_N_AGP   0x0020
#define PCI_DEVICE_ID_APPLE_UNI_N_GMAC  0x0021
#define PCI_DEVICE_ID_APPLE_UNI_N_FW2   0x0030

#define PCI_VENDOR_ID_YAMAHA            0x1073
#define PCI_DEVICE_ID_YAMAHA_724        0x0004
#define PCI_DEVICE_ID_YAMAHA_724F       0x000d
#define PCI_DEVICE_ID_YAMAHA_740        0x000a
#define PCI_DEVICE_ID_YAMAHA_740C       0x000c
#define PCI_DEVICE_ID_YAMAHA_744        0x0010
#define PCI_DEVICE_ID_YAMAHA_754        0x0012

#define PCI_VENDOR_ID_NEXGEN            0x1074
#define PCI_DEVICE_ID_NEXGEN_82C501     0x4e78

#define PCI_VENDOR_ID_QLOGIC            0x1077
#define PCI_DEVICE_ID_QLOGIC_ISP1020    0x1020
#define PCI_DEVICE_ID_QLOGIC_ISP1022    0x1022
#define PCI_DEVICE_ID_QLOGIC_ISP2100    0x2100
#define PCI_DEVICE_ID_QLOGIC_ISP2200    0x2200

#define PCI_VENDOR_ID_CYRIX             0x1078
#define PCI_DEVICE_ID_CYRIX_5510        0x0000
#define PCI_DEVICE_ID_CYRIX_PCI_MASTER  0x0001
#define PCI_DEVICE_ID_CYRIX_5520        0x0002
#define PCI_DEVICE_ID_CYRIX_5530_LEGACY 0x0100
#define PCI_DEVICE_ID_CYRIX_5530_SMI    0x0101
#define PCI_DEVICE_ID_CYRIX_5530_IDE    0x0102
#define PCI_DEVICE_ID_CYRIX_5530_AUDIO  0x0103
#define PCI_DEVICE_ID_CYRIX_5530_VIDEO  0x0104

#define PCI_VENDOR_ID_LEADTEK           0x107d
#define PCI_DEVICE_ID_LEADTEK_805       0x0000

#define PCI_VENDOR_ID_CONTAQ            0x1080
#define PCI_DEVICE_ID_CONTAQ_82C599     0x0600
#define PCI_DEVICE_ID_CONTAQ_82C693     0xc693

#define PCI_VENDOR_ID_FOREX             0x1083

#define PCI_VENDOR_ID_OLICOM            0x108d
#define PCI_DEVICE_ID_OLICOM_OC3136     0x0001
#define PCI_DEVICE_ID_OLICOM_OC2315     0x0011
#define PCI_DEVICE_ID_OLICOM_OC2325     0x0012
#define PCI_DEVICE_ID_OLICOM_OC2183     0x0013
#define PCI_DEVICE_ID_OLICOM_OC2326     0x0014
#define PCI_DEVICE_ID_OLICOM_OC6151     0x0021

#define PCI_VENDOR_ID_SUN               0x108e
#define PCI_DEVICE_ID_SUN_EBUS          0x1000
#define PCI_DEVICE_ID_SUN_HAPPYMEAL     0x1001
#define PCI_DEVICE_ID_SUN_SIMBA         0x5000
#define PCI_DEVICE_ID_SUN_PBM           0x8000
#define PCI_DEVICE_ID_SUN_SABRE         0xa000

#define PCI_VENDOR_ID_CMD               0x1095
#define PCI_DEVICE_ID_CMD_640           0x0640
#define PCI_DEVICE_ID_CMD_643           0x0643
#define PCI_DEVICE_ID_CMD_646           0x0646
#define PCI_DEVICE_ID_CMD_647           0x0647
#define PCI_DEVICE_ID_CMD_670           0x0670

#define PCI_VENDOR_ID_VISION            0x1098
#define PCI_DEVICE_ID_VISION_QD8500     0x0001
#define PCI_DEVICE_ID_VISION_QD8580     0x0002

#define PCI_VENDOR_ID_BROOKTREE         0x109e
#define PCI_DEVICE_ID_BROOKTREE_848     0x0350
#define PCI_DEVICE_ID_BROOKTREE_849A    0x0351
#define PCI_DEVICE_ID_BROOKTREE_878_1   0x036e
#define PCI_DEVICE_ID_BROOKTREE_878     0x0878
#define PCI_DEVICE_ID_BROOKTREE_8474    0x8474

#define PCI_VENDOR_ID_SIERRA            0x10a8
#define PCI_DEVICE_ID_SIERRA_STB        0x0000

#define PCI_VENDOR_ID_ACC               0x10aa
#define PCI_DEVICE_ID_ACC_2056          0x0000

#define PCI_VENDOR_ID_WINBOND           0x10ad
#define PCI_DEVICE_ID_WINBOND_83769     0x0001
#define PCI_DEVICE_ID_WINBOND_82C105    0x0105
#define PCI_DEVICE_ID_WINBOND_83C553    0x0565

#define PCI_VENDOR_ID_DATABOOK          0x10b3
#define PCI_DEVICE_ID_DATABOOK_87144    0xb106

#define PCI_VENDOR_ID_PLX               0x10b5
#define PCI_DEVICE_ID_PLX_9050          0x9050
#define PCI_DEVICE_ID_PLX_9060          0x9060
#define PCI_DEVICE_ID_PLX_9060ES        0x906E
#define PCI_DEVICE_ID_PLX_9060SD        0x906D
#define PCI_DEVICE_ID_PLX_9080          0x9080

#define PCI_VENDOR_ID_MADGE             0x10b6
#define PCI_DEVICE_ID_MADGE_MK2         0x0002
#define PCI_DEVICE_ID_MADGE_C155S       0x1001

#define PCI_VENDOR_ID_3COM              0x10b7
#define PCI_DEVICE_ID_3COM_3C985        0x0001
#define PCI_DEVICE_ID_3COM_3C339        0x3390
#define PCI_DEVICE_ID_3COM_3C590        0x5900
#define PCI_DEVICE_ID_3COM_3C595TX      0x5950
#define PCI_DEVICE_ID_3COM_3C595T4      0x5951
#define PCI_DEVICE_ID_3COM_3C595MII     0x5952
#define PCI_DEVICE_ID_3COM_3C900TPO     0x9000
#define PCI_DEVICE_ID_3COM_3C900COMBO   0x9001
#define PCI_DEVICE_ID_3COM_3C905TX      0x9050
#define PCI_DEVICE_ID_3COM_3C905T4      0x9051
#define PCI_DEVICE_ID_3COM_3C905B_TX    0x9055

#define PCI_VENDOR_ID_SMC               0x10b8
#define PCI_DEVICE_ID_SMC_EPIC100       0x0005

#define PCI_VENDOR_ID_AL                0x10b9
#define PCI_DEVICE_ID_AL_M1445          0x1445
#define PCI_DEVICE_ID_AL_M1449          0x1449
#define PCI_DEVICE_ID_AL_M1451          0x1451
#define PCI_DEVICE_ID_AL_M1461          0x1461
#define PCI_DEVICE_ID_AL_M1489          0x1489
#define PCI_DEVICE_ID_AL_M1511          0x1511
#define PCI_DEVICE_ID_AL_M1513          0x1513
#define PCI_DEVICE_ID_AL_M1521          0x1521
#define PCI_DEVICE_ID_AL_M1523          0x1523
#define PCI_DEVICE_ID_AL_M1531          0x1531
#define PCI_DEVICE_ID_AL_M1533          0x1533
#define PCI_DEVICE_ID_AL_M3307          0x3307