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00139 static const char *version = "ewrk3.c:v0.43 96/8/16 davies@maniac.ultranet.com\n";
00140
00141 #include <linux/module.h>
00142
00143 #include <linux/kernel.h>
00144 #include <linux/sched.h>
00145 #include <linux/string.h>
00146 #include <linux/ptrace.h>
00147 #include <linux/errno.h>
00148 #include <linux/ioport.h>
00149 #include <linux/malloc.h>
00150 #include <linux/interrupt.h>
00151 #include <linux/delay.h>
00152 #include <linux/init.h>
00153 #include <asm/bitops.h>
00154 #include <asm/io.h>
00155 #include <asm/dma.h>
00156 #include <asm/uaccess.h>
00157
00158 #include <linux/netdevice.h>
00159 #include <linux/etherdevice.h>
00160 #include <linux/skbuff.h>
00161
00162 #include <linux/time.h>
00163 #include <linux/types.h>
00164 #include <linux/unistd.h>
00165 #include <linux/ctype.h>
00166
00167 #include "ewrk3.h"
00168
00169 #ifdef EWRK3_DEBUG
00170 static int ewrk3_debug = EWRK3_DEBUG;
00171 #else
00172 static int ewrk3_debug = 1;
00173 #endif
00174
00175 #define EWRK3_NDA 0xffe0
00176
00177 #define PROBE_LENGTH 32
00178 #define ETH_PROM_SIG 0xAA5500FFUL
00179
00180 #ifndef EWRK3_SIGNATURE
00181 #define EWRK3_SIGNATURE {"DE203","DE204","DE205",""}
00182 #define EWRK3_STRLEN 8
00183 #endif
00184
00185 #ifndef EWRK3_RAM_BASE_ADDRESSES
00186 #define EWRK3_RAM_BASE_ADDRESSES {0xc0000,0xd0000,0x00000}
00187 #endif
00188
00189
00190
00191
00192 #define EWRK3_IO_BASE 0x100
00193 #define EWRK3_IOP_INC 0x20
00194 #define EWRK3_TOTAL_SIZE 0x20
00195
00196 #ifndef MAX_NUM_EWRK3S
00197 #define MAX_NUM_EWRK3S 21
00198 #endif
00199
00200 #ifndef EWRK3_EISA_IO_PORTS
00201 #define EWRK3_EISA_IO_PORTS 0x0c00
00202 #endif
00203
00204 #ifndef MAX_EISA_SLOTS
00205 #define MAX_EISA_SLOTS 16
00206 #define EISA_SLOT_INC 0x1000
00207 #endif
00208
00209 #define CRC_POLYNOMIAL_BE 0x04c11db7UL
00210 #define CRC_POLYNOMIAL_LE 0xedb88320UL
00211
00212 #define QUEUE_PKT_TIMEOUT (1*HZ)
00213
00214
00215
00216
00217 #define IO_ONLY 0x00
00218 #define SHMEM_2K 0x800
00219 #define SHMEM_32K 0x8000
00220 #define SHMEM_64K 0x10000
00221
00222
00223
00224
00225 #define ENABLE_IRQs { \
00226 icr |= lp->irq_mask;\
00227 outb(icr, EWRK3_ICR); \
00228 }
00229
00230 #define DISABLE_IRQs { \
00231 icr = inb(EWRK3_ICR);\
00232 icr &= ~lp->irq_mask;\
00233 outb(icr, EWRK3_ICR); \
00234 }
00235
00236
00237
00238
00239 #define START_EWRK3 { \
00240 csr = inb(EWRK3_CSR);\
00241 csr &= ~(CSR_TXD|CSR_RXD);\
00242 outb(csr, EWRK3_CSR); \
00243 }
00244
00245 #define STOP_EWRK3 { \
00246 csr = (CSR_TXD|CSR_RXD);\
00247 outb(csr, EWRK3_CSR); \
00248 }
00249
00250
00251
00252
00253 #define EWRK3_PKT_STAT_SZ 16
00254 #define EWRK3_PKT_BIN_SZ 128
00255
00256
00257 struct ewrk3_private {
00258 char adapter_name[80];
00259 u_long shmem_base;
00260 u_long shmem_length;
00261 struct net_device_stats stats;
00262 struct {
00263 u32 bins[EWRK3_PKT_STAT_SZ];
00264 u32 unicast;
00265 u32 multicast;
00266 u32 broadcast;
00267 u32 excessive_collisions;
00268 u32 tx_underruns;
00269 u32 excessive_underruns;
00270 } pktStats;
00271 u_char irq_mask;
00272 u_char mPage;
00273 u_char lemac;
00274 u_char hard_strapped;
00275 u_char lock;
00276 u_char txc;
00277 u_char *mctbl;
00278 };
00279
00280
00281
00282
00283 #define FORCE_2K_MODE { \
00284 shmem_length = SHMEM_2K;\
00285 outb(((mem_start - 0x80000) >> 11), EWRK3_MBR);\
00286 }
00287
00288
00289
00290
00291 static int ewrk3_open(struct device *dev);
00292 static int ewrk3_queue_pkt(struct sk_buff *skb, struct device *dev);
00293 static void ewrk3_interrupt(int irq, void *dev_id, struct pt_regs *regs);
00294 static int ewrk3_close(struct device *dev);
00295 static struct net_device_stats *ewrk3_get_stats(struct device *dev);
00296 static void set_multicast_list(struct device *dev);
00297 static int ewrk3_ioctl(struct device *dev, struct ifreq *rq, int cmd);
00298
00299
00300
00301
00302 static int ewrk3_hw_init(struct device *dev, u_long iobase);
00303 static void ewrk3_init(struct device *dev);
00304 static int ewrk3_rx(struct device *dev);
00305 static int ewrk3_tx(struct device *dev);
00306
00307 static void EthwrkSignature(char *name, char *eeprom_image);
00308 static int DevicePresent(u_long iobase);
00309 static void SetMulticastFilter(struct device *dev);
00310 static int EISA_signature(char *name, s32 eisa_id);
00311
00312 static int Read_EEPROM(u_long iobase, u_char eaddr);
00313 static int Write_EEPROM(short data, u_long iobase, u_char eaddr);
00314 static u_char get_hw_addr(struct device *dev, u_char * eeprom_image, char chipType);
00315
00316 static void isa_probe(struct device *dev, u_long iobase);
00317 static void eisa_probe(struct device *dev, u_long iobase);
00318 static struct device *alloc_device(struct device *dev, u_long iobase);
00319 static int ewrk3_dev_index(char *s);
00320 static struct device *insert_device(struct device *dev, u_long iobase, int (*init) (struct device *));
00321
00322
00323 #ifdef MODULE
00324 int init_module(void);
00325 void cleanup_module(void);
00326 static int autoprobed = 1, loading_module = 1;
00327
00328 #else
00329 static u_char irq[] =
00330 {5, 0, 10, 3, 11, 9, 15, 12};
00331 static int autoprobed = 0, loading_module = 0;
00332
00333 #endif
00334
00335 static char name[EWRK3_STRLEN + 1];
00336 static int num_ewrk3s = 0, num_eth = 0;
00337
00338
00339
00340
00341 #define INIT_EWRK3 {\
00342 outb(EEPROM_INIT, EWRK3_IOPR);\
00343 mdelay(1);\
00344 }
00345
00346
00347
00348
00349 __initfunc(int ewrk3_probe(struct device *dev))
00350 {
00351 int tmp = num_ewrk3s, status = -ENODEV;
00352 u_long iobase = dev->base_addr;
00353
00354 if ((iobase == 0) && loading_module) {
00355 printk("Autoprobing is not supported when loading a module based driver.\n");
00356 status = -EIO;
00357 } else {
00358
00359 isa_probe(dev, iobase);
00360 eisa_probe(dev, iobase);
00361
00362 if ((tmp == num_ewrk3s) && (iobase != 0) && loading_module) {
00363 printk("%s: ewrk3_probe() cannot find device at 0x%04lx.\n", dev->name,
00364 iobase);
00365 }
00366
00367
00368
00369
00370 for (; (dev->priv == NULL) && (dev->next != NULL); dev = dev->next);
00371
00372 if (dev->priv)
00373 status = 0;
00374 if (iobase == 0)
00375 autoprobed = 1;
00376 }
00377
00378 return status;
00379 }
00380
00381 __initfunc(static int
00382 ewrk3_hw_init(struct device *dev, u_long iobase))
00383 {
00384 struct ewrk3_private *lp;
00385 int i, status = 0;
00386 u_long mem_start, shmem_length;
00387 u_char cr, cmr, icr, nicsr, lemac, hard_strapped = 0;
00388 u_char eeprom_image[EEPROM_MAX], chksum, eisa_cr = 0;
00389
00390
00391
00392
00393
00394 if (iobase > 0x400)
00395 eisa_cr = inb(EISA_CR);
00396 INIT_EWRK3;
00397
00398 nicsr = inb(EWRK3_CSR);
00399
00400 icr = inb(EWRK3_ICR);
00401 icr &= 0x70;
00402 outb(icr, EWRK3_ICR);
00403
00404 if (nicsr == (CSR_TXD | CSR_RXD)) {
00405
00406
00407 for (chksum = 0, i = 0; i < EEPROM_MAX; i += 2) {
00408 union {
00409 short val;
00410 char c[2];
00411 } tmp;
00412
00413 tmp.val = (short) Read_EEPROM(iobase, (i >> 1));
00414 eeprom_image[i] = tmp.c[0];
00415 eeprom_image[i + 1] = tmp.c[1];
00416 chksum += eeprom_image[i] + eeprom_image[i + 1];
00417 }
00418
00419 if (chksum != 0) {
00420 printk("%s: Device has a bad on-board EEPROM.\n", dev->name);
00421 status = -ENXIO;
00422 } else {
00423 EthwrkSignature(name, eeprom_image);
00424 if (*name != '\0') {
00425 dev->base_addr = iobase;
00426
00427 if (iobase > 0x400) {
00428 outb(eisa_cr, EISA_CR);
00429 }
00430 lemac = eeprom_image[EEPROM_CHIPVER];
00431 cmr = inb(EWRK3_CMR);
00432
00433 if (((lemac == LeMAC) && ((cmr & CMR_NO_EEPROM) != CMR_NO_EEPROM)) ||
00434 ((lemac == LeMAC2) && !(cmr & CMR_HS))) {
00435 printk("%s: %s at %#4lx", dev->name, name, iobase);
00436 hard_strapped = 1;
00437 } else if ((iobase & 0x0fff) == EWRK3_EISA_IO_PORTS) {
00438
00439 printk("%s: %s at %#4lx (EISA slot %ld)",
00440 dev->name, name, iobase, ((iobase >> 12) & 0x0f));
00441 } else {
00442 printk("%s: %s at %#4lx", dev->name, name, iobase);
00443 }
00444
00445 if (!status) {
00446 printk(", h/w address ");
00447 if (lemac != LeMAC2)
00448 DevicePresent(iobase);
00449 status = get_hw_addr(dev, eeprom_image, lemac);
00450 for (i = 0; i < ETH_ALEN - 1; i++) {
00451 printk("%2.2x:", dev->dev_addr[i]);
00452 }
00453 printk("%2.2x,\n", dev->dev_addr[i]);
00454
00455 if (status) {
00456 printk(" which has an EEPROM CRC error.\n");
00457 status = -ENXIO;
00458 } else {
00459 if (lemac == LeMAC2) {
00460 cmr &= ~(CMR_RA | CMR_WB | CMR_LINK | CMR_POLARITY | CMR_0WS);
00461 if (eeprom_image[EEPROM_MISC0] & READ_AHEAD)
00462 cmr |= CMR_RA;
00463 if (eeprom_image[EEPROM_MISC0] & WRITE_BEHIND)
00464 cmr |= CMR_WB;
00465 if (eeprom_image[EEPROM_NETMAN0] & NETMAN_POL)
00466 cmr |= CMR_POLARITY;
00467 if (eeprom_image[EEPROM_NETMAN0] & NETMAN_LINK)
00468 cmr |= CMR_LINK;
00469 if (eeprom_image[EEPROM_MISC0] & _0WS_ENA)
00470 cmr |= CMR_0WS;
00471 }
00472 if (eeprom_image[EEPROM_SETUP] & SETUP_DRAM)
00473 cmr |= CMR_DRAM;
00474 outb(cmr, EWRK3_CMR);
00475
00476 cr = inb(EWRK3_CR);
00477 cr |= eeprom_image[EEPROM_SETUP] & SETUP_APD;
00478 if (cr & SETUP_APD)
00479 cr |= eeprom_image[EEPROM_SETUP] & SETUP_PS;
00480 cr |= eeprom_image[EEPROM_MISC0] & FAST_BUS;
00481 cr |= eeprom_image[EEPROM_MISC0] & ENA_16;
00482 outb(cr, EWRK3_CR);
00483
00484
00485
00486
00487
00488 mem_start = inb(EWRK3_MBR);
00489 shmem_length = 0;
00490 if (mem_start != 0) {
00491 if ((mem_start >= 0x0a) && (mem_start <= 0x0f)) {
00492 mem_start *= SHMEM_64K;
00493 shmem_length = SHMEM_64K;
00494 } else if ((mem_start >= 0x14) && (mem_start <= 0x1f)) {
00495 mem_start *= SHMEM_32K;
00496 shmem_length = SHMEM_32K;
00497 } else if ((mem_start >= 0x40) && (mem_start <= 0xff)) {
00498 mem_start = mem_start * SHMEM_2K + 0x80000;
00499 shmem_length = SHMEM_2K;
00500 } else {
00501 status = -ENXIO;
00502 }
00503 }
00504
00505
00506
00507
00508
00509
00510 if (!status) {
00511 if (hard_strapped) {
00512 printk(" is hard strapped.\n");
00513 } else if (mem_start) {
00514 printk(" has a %dk RAM window", (int) (shmem_length >> 10));
00515 printk(" at 0x%.5lx", mem_start);
00516 } else {
00517 printk(" is in I/O only mode");
00518 }
00519
00520
00521 dev->priv = (void *) kmalloc(sizeof(struct ewrk3_private),
00522 GFP_KERNEL);
00523 if (dev->priv == NULL) {
00524 return -ENOMEM;
00525 }
00526 lp = (struct ewrk3_private *) dev->priv;
00527 memset(dev->priv, 0, sizeof(struct ewrk3_private));
00528 lp->shmem_base = mem_start;
00529 lp->shmem_length = shmem_length;
00530 lp->lemac = lemac;
00531 lp->hard_strapped = hard_strapped;
00532
00533 lp->mPage = 64;
00534 if (cmr & CMR_DRAM)
00535 lp->mPage <<= 1;
00536
00537 sprintf(lp->adapter_name, "%s (%s)", name, dev->name);
00538 request_region(iobase, EWRK3_TOTAL_SIZE, lp->adapter_name);
00539
00540 lp->irq_mask = ICR_TNEM | ICR_TXDM | ICR_RNEM | ICR_RXDM;
00541
00542 if (!hard_strapped) {
00543
00544
00545
00546 icr |= ICR_IE;
00547 outb(icr, EWRK3_ICR);
00548
00549
00550 dev->dma = 0;
00551
00552
00553
00554 if (dev->irq < 2) {
00555 #ifndef MODULE
00556 u_char irqnum;
00557
00558 autoirq_setup(0);
00559
00560
00561
00562
00563 icr |= ICR_TNEM;
00564 outb(1, EWRK3_TDQ);
00565 outb(icr, EWRK3_ICR);
00566
00567 irqnum = irq[((icr & IRQ_SEL) >> 4)];
00568
00569 dev->irq = autoirq_report(1);
00570 if ((dev->irq) && (irqnum == dev->irq)) {
00571 printk(" and uses IRQ%d.\n", dev->irq);
00572 } else {
00573 if (!dev->irq) {
00574 printk(" and failed to detect IRQ line.\n");
00575 } else if ((irqnum == 1) && (lemac == LeMAC2)) {
00576 printk(" and an illegal IRQ line detected.\n");
00577 } else {
00578 printk(", but incorrect IRQ line detected.\n");
00579 }
00580 status = -ENXIO;
00581 }
00582
00583 DISABLE_IRQs;
00584
00585 #endif
00586 } else {
00587 printk(" and requires IRQ%d.\n", dev->irq);
00588 }
00589 }
00590 if (status)
00591 release_region(iobase, EWRK3_TOTAL_SIZE);
00592 } else {
00593 status = -ENXIO;
00594 }
00595 }
00596 }
00597 } else {
00598 status = -ENXIO;
00599 }
00600 }
00601
00602 if (!status) {
00603 if (ewrk3_debug > 1) {
00604 printk(version);
00605 }
00606
00607 dev->open = &ewrk3_open;
00608 dev->hard_start_xmit = &ewrk3_queue_pkt;
00609 dev->stop = &ewrk3_close;
00610 dev->get_stats = &ewrk3_get_stats;
00611 dev->set_multicast_list = &set_multicast_list;
00612 dev->do_ioctl = &ewrk3_ioctl;
00613
00614 dev->mem_start = 0;
00615
00616
00617 ether_setup(dev);
00618 }
00619 } else {
00620 status = -ENXIO;
00621 }
00622
00623 return status;
00624 }
00625
00626
00627 static int ewrk3_open(struct device *dev)
00628 {
00629 struct ewrk3_private *lp = (struct ewrk3_private *) dev->priv;
00630 u_long iobase = dev->base_addr;
00631 int i, status = 0;
00632 u_char icr, csr;
00633
00634
00635
00636
00637 STOP_EWRK3;
00638
00639 if (!lp->hard_strapped) {
00640 if (request_irq(dev->irq, (void *) ewrk3_interrupt, 0, "ewrk3", dev)) {
00641 printk("ewrk3_open(): Requested IRQ%d is busy\n", dev->irq);
00642 status = -EAGAIN;
00643 } else {
00644
00645
00646
00647
00648 ewrk3_init(dev);
00649
00650 if (ewrk3_debug > 1) {
00651 printk("%s: ewrk3 open with irq %d\n", dev->name, dev->irq);
00652 printk(" physical address: ");
00653 for (i = 0; i < 5; i++) {
00654 printk("%2.2x:", (u_char) dev->dev_addr[i]);
00655 }
00656 printk("%2.2x\n", (u_char) dev->dev_addr[i]);
00657 if (lp->shmem_length == 0) {
00658 printk(" no shared memory, I/O only mode\n");
00659 } else {
00660 printk(" start of shared memory: 0x%08lx\n", lp->shmem_base);
00661 printk(" window length: 0x%04lx\n", lp->shmem_length);
00662 }
00663 printk(" # of DRAMS: %d\n", ((inb(EWRK3_CMR) & 0x02) ? 2 : 1));
00664 printk(" csr: 0x%02x\n", inb(EWRK3_CSR));
00665 printk(" cr: 0x%02x\n", inb(EWRK3_CR));
00666 printk(" icr: 0x%02x\n", inb(EWRK3_ICR));
00667 printk(" cmr: 0x%02x\n", inb(EWRK3_CMR));
00668 printk(" fmqc: 0x%02x\n", inb(EWRK3_FMQC));
00669 }
00670 dev->tbusy = 0;
00671 dev->start = 1;
00672 dev->interrupt = UNMASK_INTERRUPTS;
00673
00674
00675
00676
00677 icr = inb(EWRK3_ICR);
00678 ENABLE_IRQs;
00679
00680 }
00681 } else {
00682 dev->start = 0;
00683 dev->tbusy = 1;
00684 printk("%s: ewrk3 available for hard strapped set up only.\n", dev->name);
00685 printk(" Run the 'ewrk3setup' utility or remove the hard straps.\n");
00686 }
00687
00688 MOD_INC_USE_COUNT;
00689
00690 return status;
00691 }
00692
00693
00694
00695
00696 static void ewrk3_init(struct device *dev)
00697 {
00698 struct ewrk3_private *lp = (struct ewrk3_private *) dev->priv;
00699 u_char csr, page;
00700 u_long iobase = dev->base_addr;
00701
00702
00703
00704
00705 set_multicast_list(dev);
00706
00707
00708
00709
00710 while (inb(EWRK3_TQ));
00711 while (inb(EWRK3_TDQ));
00712 while (inb(EWRK3_RQ));
00713 while (inb(EWRK3_FMQ));
00714
00715
00716
00717
00718 for (page = 1; page < lp->mPage; page++) {
00719 outb(page, EWRK3_FMQ);
00720 }
00721
00722 lp->lock = 0;
00723
00724 START_EWRK3;
00725 }
00726
00727
00728
00729
00730 static int ewrk3_queue_pkt(struct sk_buff *skb, struct device *dev)
00731 {
00732 struct ewrk3_private *lp = (struct ewrk3_private *) dev->priv;
00733 u_long iobase = dev->base_addr;
00734 int status = 0;
00735 u_char icr, csr;
00736
00737
00738 if (dev->tbusy || lp->lock) {
00739 int tickssofar = jiffies - dev->trans_start;
00740 if (tickssofar < QUEUE_PKT_TIMEOUT) {
00741 status = -1;
00742 } else if (!lp->hard_strapped) {
00743 printk("%s: transmit timed/locked out, status %04x, resetting.\n",
00744 dev->name, inb(EWRK3_CSR));
00745
00746
00747
00748
00749 DISABLE_IRQs;
00750
00751
00752
00753
00754 STOP_EWRK3;
00755
00756 ewrk3_init(dev);
00757
00758
00759
00760
00761 ENABLE_IRQs;
00762
00763 dev->tbusy = 0;
00764 dev->trans_start = jiffies;
00765 }
00766 } else if (skb->len > 0) {
00767
00768
00769
00770
00771
00772 if (test_and_set_bit(0, (void *) &dev->tbusy) != 0)
00773 printk("%s: Transmitter access conflict.\n", dev->name);
00774
00775 DISABLE_IRQs;
00776
00777
00778
00779
00780 if (inb(EWRK3_FMQC) > 0) {
00781 u_long buf = 0;
00782 u_char page;
00783
00784 if ((page = inb(EWRK3_FMQ)) < lp->mPage) {
00785
00786
00787
00788 while (test_and_set_bit(0, (void *) &lp->lock) != 0);
00789 if (lp->shmem_length == IO_ONLY) {
00790 outb(page, EWRK3_IOPR);
00791 } else if (lp->shmem_length == SHMEM_2K) {
00792 buf = lp->shmem_base;
00793 outb(page, EWRK3_MPR);
00794 } else if (lp->shmem_length == SHMEM_32K) {
00795 buf = ((((short) page << 11) & 0x7800) + lp->shmem_base);
00796 outb((page >> 4), EWRK3_MPR);
00797 } else if (lp->shmem_length == SHMEM_64K) {
00798 buf = ((((short) page << 11) & 0xf800) + lp->shmem_base);
00799 outb((page >> 5), EWRK3_MPR);
00800 } else {
00801 status = -1;
00802 printk("%s: Oops - your private data area is hosed!\n", dev->name);
00803 }
00804
00805 if (!status) {
00806
00807
00808
00809
00810
00811
00812 if (lp->shmem_length == IO_ONLY) {
00813 int i;
00814 u_char *p = skb->data;
00815
00816 outb((char) (TCR_QMODE | TCR_PAD | TCR_IFC), EWRK3_DATA);
00817 outb((char) (skb->len & 0xff), EWRK3_DATA);
00818 outb((char) ((skb->len >> 8) & 0xff), EWRK3_DATA);
00819 outb((char) 0x04, EWRK3_DATA);
00820 for (i = 0; i < skb->len; i++) {
00821 outb(*p++, EWRK3_DATA);
00822 }
00823 outb(page, EWRK3_TQ);
00824 } else {
00825 writeb((char) (TCR_QMODE | TCR_PAD | TCR_IFC), (char *) buf);
00826 buf += 1;
00827 writeb((char) (skb->len & 0xff), (char *) buf);
00828 buf += 1;
00829 if (lp->txc) {
00830 writeb((char) (((skb->len >> 8) & 0xff) | XCT), (char *) buf);
00831 buf += 1;
00832 writeb(0x04, (char *) buf);
00833 buf += 1;
00834 writeb(0x00, (char *) (buf + skb->len));
00835 memcpy_toio(buf, skb->data, PRELOAD);
00836 outb(page, EWRK3_TQ);
00837 memcpy_toio(buf + PRELOAD, skb->data + PRELOAD, skb->len - PRELOAD);
00838 writeb(0xff, (char *) (buf + skb->len));
00839 } else {
00840 writeb((char) ((skb->len >> 8) & 0xff), (char *) buf);
00841 buf += 1;
00842 writeb(0x04, (char *) buf);
00843 buf += 1;
00844 memcpy_toio((char *) buf, skb->data, skb->len);
00845 outb(page, EWRK3_TQ);
00846 }
00847 }
00848
00849 lp->stats.tx_bytes += skb->len;
00850 dev->trans_start = jiffies;
00851 dev_kfree_skb(skb);
00852 } else {
00853 outb(page, EWRK3_FMQ);
00854 }
00855 lp->lock = 0;
00856 } else {
00857 printk("ewrk3_queue_pkt(): Invalid free memory page (%d).\n",
00858 (u_char) page);
00859 }
00860 } else {
00861 printk("ewrk3_queue_pkt(): No free resources...\n");
00862 printk("ewrk3_queue_pkt(): CSR: %02x ICR: %02x FMQC: %02x\n", inb(EWRK3_CSR), inb(EWRK3_ICR), inb(EWRK3_FMQC));
00863 }
00864
00865
00866 if (inb(EWRK3_FMQC) > 0) {
00867 dev->tbusy = 0;
00868 }
00869 ENABLE_IRQs;
00870 }
00871 return status;
00872 }
00873
00874
00875
00876
00877 static void ewrk3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
00878 {
00879 struct device *dev = dev_id;
00880 struct ewrk3_private *lp;
00881 u_long iobase;
00882 u_char icr, cr, csr;
00883
00884 if (dev == NULL) {
00885 printk("ewrk3_interrupt(): irq %d for unknown device.\n", irq);
00886 } else {
00887 lp = (struct ewrk3_private *) dev->priv;
00888 iobase = dev->base_addr;
00889
00890 if (dev->interrupt)
00891 printk("%s: Re-entering the interrupt handler.\n", dev->name);
00892
00893 dev->interrupt = MASK_INTERRUPTS;
00894
00895
00896 csr = inb(EWRK3_CSR);
00897
00898
00899
00900
00901 DISABLE_IRQs;
00902
00903 cr = inb(EWRK3_CR);
00904 cr |= CR_LED;
00905 outb(cr, EWRK3_CR);
00906
00907 if (csr & CSR_RNE)
00908 ewrk3_rx(dev);
00909
00910 if (csr & CSR_TNE)
00911 ewrk3_tx(dev);
00912
00913
00914
00915
00916
00917
00918
00919 if (inb(EWRK3_FMQC)) {
00920 lp->irq_mask |= ICR_TXDM | ICR_RXDM;
00921 csr &= ~(CSR_TXD | CSR_RXD);
00922 outb(csr, EWRK3_CSR);
00923 dev->tbusy = 0;
00924 mark_bh(NET_BH);
00925 } else {
00926 lp->irq_mask &= ~(ICR_TXDM | ICR_RXDM);
00927 }
00928
00929
00930 cr &= ~CR_LED;
00931 outb(cr, EWRK3_CR);
00932
00933 dev->interrupt = UNMASK_INTERRUPTS;
00934 ENABLE_IRQs;
00935 }
00936
00937 return;
00938 }
00939
00940 static int ewrk3_rx(struct device *dev)
00941 {
00942 struct ewrk3_private *lp = (struct ewrk3_private *) dev->priv;
00943 u_long iobase = dev->base_addr;
00944 int i, status = 0;
00945 u_char page, tmpPage = 0, tmpLock = 0;
00946 u_long buf = 0;
00947
00948 while (inb(EWRK3_RQC) && !status) {
00949 if ((page = inb(EWRK3_RQ)) < lp->mPage) {
00950
00951
00952
00953
00954 if ((tmpLock = test_and_set_bit(0, (void *) &lp->lock)) == 1) {
00955 if (lp->shmem_length == IO_ONLY) {
00956 tmpPage = inb(EWRK3_IOPR);
00957 } else {
00958 tmpPage = inb(EWRK3_MPR);
00959 }
00960 }
00961
00962
00963
00964 if (lp->shmem_length == IO_ONLY) {
00965 outb(page, EWRK3_IOPR);
00966 } else if (lp->shmem_length == SHMEM_2K) {
00967 buf = lp->shmem_base;
00968 outb(page, EWRK3_MPR);
00969 } else if (lp->shmem_length == SHMEM_32K) {
00970 buf = ((((short) page << 11) & 0x7800) + lp->shmem_base);
00971 outb((page >> 4), EWRK3_MPR);
00972 } else if (lp->shmem_length == SHMEM_64K) {
00973 buf = ((((short) page << 11) & 0xf800) + lp->shmem_base);
00974 outb((page >> 5), EWRK3_MPR);
00975 } else {
00976 status = -1;
00977 printk("%s: Oops - your private data area is hosed!\n", dev->name);
00978 }
00979
00980 if (!status) {
00981 char rx_status;
00982 int pkt_len;
00983
00984 if (lp->shmem_length == IO_ONLY) {
00985 rx_status = inb(EWRK3_DATA);
00986 pkt_len = inb(EWRK3_DATA);
00987 pkt_len |= ((u_short) inb(EWRK3_DATA) << 8);
00988 } else {
00989 rx_status = readb(buf);
00990 buf += 1;
00991 pkt_len = readw(buf);
00992 buf += 3;
00993 }
00994
00995 if (!(rx_status & R_ROK)) {
00996 lp->stats.rx_errors++;
00997 if (rx_status & R_DBE)
00998 lp->stats.rx_frame_errors++;
00999 if (rx_status & R_CRC)
01000 lp->stats.rx_crc_errors++;
01001 if (rx_status & R_PLL)
01002 lp->stats.rx_fifo_errors++;
01003 } else {
01004 struct sk_buff *skb;
01005
01006 if ((skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
01007 unsigned char *p;
01008 skb->dev = dev;
01009 skb_reserve(skb, 2);
01010 p = skb_put(skb, pkt_len);
01011
01012 if (lp->shmem_length == IO_ONLY) {
01013 *p = inb(EWRK3_DATA);
01014 for (i = 0; i < pkt_len; i++) {
01015 *p++ = inb(EWRK3_DATA);
01016 }
01017 } else {
01018 memcpy_fromio(p, buf, pkt_len);
01019 }
01020
01021
01022
01023
01024
01025 skb->protocol = eth_type_trans(skb, dev);
01026 netif_rx(skb);
01027
01028
01029
01030
01031 lp->stats.rx_packets++;
01032 lp->stats.rx_bytes += pkt_len;
01033 for (i = 1; i < EWRK3_PKT_STAT_SZ - 1; i++) {
01034 if (pkt_len < i * EWRK3_PKT_BIN_SZ) {
01035 lp->pktStats.bins[i]++;
01036 i = EWRK3_PKT_STAT_SZ;
01037 }
01038 }
01039 p = skb->data;
01040 if (p[0] & 0x01) {
01041 if ((*(s32 *) & p[0] == -1) && (*(s16 *) & p[4] == -1)) {
01042 lp->pktStats.broadcast++;
01043 } else {
01044 lp->pktStats.multicast++;
01045 }
01046 } else if ((*(s32 *) & p[0] == *(s32 *) & dev->dev_addr[0]) &&
01047 (*(s16 *) & p[4] == *(s16 *) & dev->dev_addr[4])) {
01048 lp->pktStats.unicast++;
01049 }
01050 lp->pktStats.bins[0]++;
01051 if (lp->pktStats.bins[0] == 0) {
01052 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
01053 }
01054 } else {
01055 printk("%s: Insufficient memory; nuking packet.\n", dev->name);
01056 lp->stats.rx_dropped++;
01057 break;
01058 }
01059 }
01060 }
01061
01062
01063
01064 outb(page, EWRK3_FMQ);
01065
01066 if (tmpLock) {
01067 if (lp->shmem_length == IO_ONLY) {
01068 outb(tmpPage, EWRK3_IOPR);
01069 } else {
01070 outb(tmpPage, EWRK3_MPR);
01071 }
01072 }
01073 lp->lock = 0;
01074 } else {
01075 printk("ewrk3_rx(): Illegal page number, page %d\n", page);
01076 printk("ewrk3_rx(): CSR: %02x ICR: %02x FMQC: %02x\n", inb(EWRK3_CSR), inb(EWRK3_ICR), inb(EWRK3_FMQC));
01077 }
01078 }
01079 return status;
01080 }
01081
01082
01083
01084
01085 static int ewrk3_tx(struct device *dev)
01086 {
01087 struct ewrk3_private *lp = (struct ewrk3_private *) dev->priv;
01088 u_long iobase = dev->base_addr;
01089 u_char tx_status;
01090
01091 while ((tx_status = inb(EWRK3_TDQ)) > 0) {
01092 if (tx_status & T_VSTS) {
01093 if (tx_status & T_TXE) {
01094 lp->stats.tx_errors++;
01095 if (tx_status & T_NCL)
01096 lp->stats.tx_carrier_errors++;
01097 if (tx_status & T_LCL)
01098 lp->stats.tx_window_errors++;
01099 if (tx_status & T_CTU) {
01100 if ((tx_status & T_COLL) ^ T_XUR) {
01101 lp->pktStats.tx_underruns++;
01102