epic100.c

Go to the documentation of this file.

/* epic100.c: A SMC 83c170 EPIC/100 Fast Ethernet driver for Linux. */
/*
        Written/copyright 1997-1999 by Donald Becker.

        This software may be used and distributed according to the terms
        of the GNU Public License, incorporated herein by reference.
        All other rights reserved.

        This driver is for the SMC83c170/175 "EPIC" series, as used on the
        SMC EtherPower II 9432 PCI adapter, and several CardBus cards.

        The author may be reached as becker@CESDIS.gsfc.nasa.gov, or C/O
        USRA Center of Excellence in Space Data and Information Sciences
           Code 930.5, Goddard Space Flight Center, Greenbelt MD 20771

        Information and updates available at
        http://cesdis.gsfc.nasa.gov/linux/drivers/epic100.html
*/

static const char *version =
"epic100.c:v1.07h 8/18/99 Donald Becker http://cesdis.gsfc.nasa.gov/linux/drivers/epic100.html\n";

/* User-tunable values. */

static int debug = 1;
#define epic_debug debug

/* Used to pass the full-duplex flag, etc. */
#define MAX_UNITS 8
static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
   Setting to > 1518 effectively disables this feature. */
static int rx_copybreak = 200;

/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
static int max_interrupt_work = 32;

/* Operational parameters that usually are not changed. */
/* Keep the ring sizes a power of two for efficiency.
   Making the Tx ring too large decreases the effectiveness of channel
   bonding and packet priority.
   There are no ill effects from too-large receive rings. */
#define TX_RING_SIZE    16
#define RX_RING_SIZE    32

/* Time in jiffies before concluding the transmitter is hung. */
#define TX_TIMEOUT  (2*HZ)

#define PKT_BUF_SZ              1536                    /* Size of each temporary Rx buffer.*/

/* Bytes transferred to chip before transmission starts. */
/* Initial threshold, increased on underflow, rounded down to 4 byte units. */
#define TX_FIFO_THRESH 256
#define RX_FIFO_THRESH 1                /* 0-3, 0==32, 64,96, or 3==128 bytes  */

#include <linux/config.h>
#include <linux/version.h>              /* Evil, but neccessary */
#include <linux/module.h>

#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/timer.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/malloc.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/delay.h>

#include <asm/processor.h>              /* Processor type for cache alignment. */
#include <asm/bitops.h>
#include <asm/io.h>
#include <asm/spinlock.h>

#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>

/* Kernel compatibility defines, common to David Hind's PCMCIA package.
   This is only in the support-all-kernels source code. */

#if ! defined (LINUX_VERSION_CODE) || LINUX_VERSION_CODE < 0x20000
#warning This driver version is only for kernel versions 2.0.0 and later.
#endif

#define RUN_AT(x) (jiffies + (x))

MODULE_AUTHOR("Donald Becker <becker@cesdis.gsfc.nasa.gov>");
MODULE_DESCRIPTION("SMC 83c170 EPIC series Ethernet driver");
MODULE_PARM(debug, "i");
MODULE_PARM(options, "1-" __MODULE_STRING(8) "i");
MODULE_PARM(full_duplex, "1-" __MODULE_STRING(8) "i");
MODULE_PARM(rx_copybreak, "i");
MODULE_PARM(max_interrupt_work, "i");

static char kernel_version[] = UTS_RELEASE;

/* The I/O extent. */
#define EPIC_TOTAL_SIZE 0x100

/*
                                Theory of Operation

I. Board Compatibility

This device driver is designed for the SMC "EPIC/100", the SMC
single-chip Ethernet controllers for PCI.  This chip is used on
the SMC EtherPower II boards.

II. Board-specific settings

PCI bus devices are configured by the system at boot time, so no jumpers
need to be set on the board.  The system BIOS will assign the
PCI INTA signal to a (preferably otherwise unused) system IRQ line.
Note: Kernel versions earlier than 1.3.73 do not support shared PCI
interrupt lines.

III. Driver operation

IIIa. Ring buffers

IVb. References

http://www.smsc.com/main/datasheets/83c171.pdf
http://www.smsc.com/main/datasheets/83c175.pdf
http://cesdis.gsfc.nasa.gov/linux/misc/NWay.html
http://www.national.com/pf/DP/DP83840A.html

IVc. Errata

*/

/* The rest of these values should never change. */

static struct device *epic_probe1(int pci_bus, int pci_devfn,

                                                                  struct device *dev, long ioaddr, int irq,
                                                                  int chip_id, int card_idx);
                                                                  
/* For 2.2 resource management we are kind of stuck with this */
#define USE_IO

                                                                  
#ifdef USE_IO
#define EPIC_USE_IO
#define EPIC_IOTYPE PCI_USES_MASTER|PCI_USES_IO|PCI_ADDR0
#else
#define EPIC_IOTYPE PCI_USES_MASTER|PCI_USES_MEM|PCI_ADDR1
#endif

enum pci_flags_bit {
        PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
        PCI_ADDR0=0x10<<0, PCI_ADDR1=0x10<<1, PCI_ADDR2=0x10<<2, PCI_ADDR3=0x10<<3,
};

struct chip_info {
        const char *name;
        u16     vendor_id, device_id, device_id_mask, pci_flags;
        int io_size, min_latency;
        struct device *(*probe1)(int pci_bus, int pci_devfn, struct device *dev,
                                                         long ioaddr, int irq, int chip_idx, int fnd_cnt);
} static chip_tbl[] = {
        {"SMSC EPIC/100 83c170", 0x10B8, 0x0005, 0x7fff,
         EPIC_IOTYPE, EPIC_TOTAL_SIZE, 32, epic_probe1},
        {"SMSC EPIC/C 83c175", 0x10B8, 0x0006, 0x7fff,
         EPIC_IOTYPE, EPIC_TOTAL_SIZE, 32, epic_probe1},
        {0,},
};

/* This matches the table above. */
static enum { MII_PWRDWN=1, TYPE2_INTR=2 } chip_features[] ={
        TYPE2_INTR, TYPE2_INTR | MII_PWRDWN, };

#ifndef USE_IO
#undef inb
#undef inw
#undef inl
#undef outb
#undef outw
#undef outl
#define inb readb
#define inw readw
#define inl readl
#define outb writeb
#define outw writew
#define outl writel
#endif

/* Offsets to registers, using the (ugh) SMC names. */
enum epic_registers {
  COMMAND=0, INTSTAT=4, INTMASK=8, GENCTL=0x0C, NVCTL=0x10, EECTL=0x14,
  PCIBurstCnt=0x18,
  TEST1=0x1C, CRCCNT=0x20, ALICNT=0x24, MPCNT=0x28,     /* Rx error counters. */
  MIICtrl=0x30, MIIData=0x34, MIICfg=0x38,
  LAN0=64,                                              /* MAC address. */
  MC0=80,                                               /* Multicast filter table. */
  RxCtrl=96, TxCtrl=112, TxSTAT=0x74,
  PRxCDAR=0x84, RxSTAT=0xA4, EarlyRx=0xB0, PTxCDAR=0xC4, TxThresh=0xDC,
};

/* Interrupt register bits, using my own meaningful names. */
enum IntrStatus {
        TxIdle=0x40000, RxIdle=0x20000, IntrSummary=0x010000,
        PCIBusErr170=0x7000, PCIBusErr175=0x1000, PhyEvent175=0x8000,
        RxStarted=0x0800, RxEarlyWarn=0x0400, CntFull=0x0200, TxUnderrun=0x0100,
        TxEmpty=0x0080, TxDone=0x0020, RxError=0x0010,
        RxOverflow=0x0008, RxFull=0x0004, RxHeader=0x0002, RxDone=0x0001,
};
enum CommandBits {
        StopRx=1, StartRx=2, TxQueued=4, RxQueued=8,
        StopTxDMA=0x20, StopRxDMA=0x40, RestartTx=0x80,
};

static u16 media2miictl[16] = {
        0, 0x0C00, 0x0C00, 0x2000,  0x0100, 0x2100, 0, 0,
        0, 0, 0, 0,  0, 0, 0, 0 };

/* The EPIC100 Rx and Tx buffer descriptors. */

struct epic_tx_desc {
        s16 status;
        u16 txlength;
        u32 bufaddr;
        u16 buflength;
        u16 control;
        u32 next;
};

struct epic_rx_desc {
        s16 status;
        u16 rxlength;
        u32 bufaddr;
        u32 buflength;
        u32 next;
};

struct epic_private {
        char devname[8];                        /* Used only for kernel debugging. */
        const char *product_name;
        struct device *next_module;

        /* Tx and Rx rings here so that they remain paragraph aligned. */
        struct epic_rx_desc rx_ring[RX_RING_SIZE];
        struct epic_tx_desc tx_ring[TX_RING_SIZE];
        /* The saved address of a sent-in-place packet/buffer, for skfree(). */
        struct sk_buff* tx_skbuff[TX_RING_SIZE];
        /* The addresses of receive-in-place skbuffs. */
        struct sk_buff* rx_skbuff[RX_RING_SIZE];

        /* Ring pointers. */
        spinlock_t lock;                                /* Group with Tx control cache line. */
        unsigned int cur_tx, dirty_tx;
        struct descriptor  *last_tx_desc;
        unsigned int cur_rx, dirty_rx;
        struct descriptor  *last_rx_desc;
        long last_rx_time;                              /* Last Rx, in jiffies. */

        u8 pci_bus, pci_dev_fn;                         /* PCI bus location. */
        u16 chip_flags;

        struct net_device_stats stats;
        struct timer_list timer;                        /* Media selection timer. */
        int tx_threshold;
        unsigned char mc_filter[8];
        signed char phys[4];                            /* MII device addresses. */
        int mii_phy_cnt;
        unsigned int tx_full:1;                         /* The Tx queue is full. */
        unsigned int full_duplex:1;                     /* Current duplex setting. */
        unsigned int force_fd:1;                        /* Full-duplex operation requested. */
        unsigned int default_port:4;            /* Last dev->if_port value. */
        unsigned int media2:4;                          /* Secondary monitored media port. */
        unsigned int medialock:1;                       /* Don't sense media type. */
        unsigned int mediasense:1;                      /* Media sensing in progress. */
        int pad0, pad1;                                         /* Used for 8-byte alignment */
};

static int epic_open(struct device *dev);
static int read_eeprom(long ioaddr, int location);
static int mdio_read(long ioaddr, int phy_id, int location);
static void mdio_write(long ioaddr, int phy_id, int location, int value);
static void epic_restart(struct device *dev);
static void epic_timer(unsigned long data);
static void epic_tx_timeout(struct device *dev);
static void epic_init_ring(struct device *dev);
static int epic_start_xmit(struct sk_buff *skb, struct device *dev);
static int epic_rx(struct device *dev);
static void epic_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
static int mii_ioctl(struct device *dev, struct ifreq *rq, int cmd);
static int epic_close(struct device *dev);
static struct net_device_stats *epic_get_stats(struct device *dev);
static void set_rx_mode(struct device *dev);


/* A list of all installed EPIC devices, for removing the driver module. */
static struct device *root_epic_dev = NULL;

#if !defined(CARDBUS)  && !defined(HAS_PCI_NETIF)
int epic100_probe(struct device *dev)
{
        int cards_found = 0;
        int chip_idx, irq, pci_flags;
        u16 pci_command, new_command;
        unsigned char pci_bus, pci_device_fn;
        long ioaddr;

        struct pci_dev *pcidev = NULL;
        while ((pcidev = pci_find_class(PCI_CLASS_NETWORK_ETHERNET << 8, pcidev))
                        != NULL) {
                long pciaddr;
                int vendor = pcidev->vendor;
                int device = pcidev->device;

                for (chip_idx = 0; chip_tbl[chip_idx].vendor_id; chip_idx++)
                        if (vendor == chip_tbl[chip_idx].vendor_id
                                && (device & chip_tbl[chip_idx].device_id_mask) ==
                                chip_tbl[chip_idx].device_id)
                                break;
                if (chip_tbl[chip_idx].vendor_id == 0)          /* Compiled out! */
                        continue;

                pci_flags = chip_tbl[chip_idx].pci_flags;
                pciaddr = pcidev->base_address[pci_flags & PCI_ADDR0 ? 0 : 1];
                pci_bus = pcidev->bus->number;
                pci_device_fn = pcidev->devfn;
                irq = pcidev->irq;

                if ((pciaddr & PCI_BASE_ADDRESS_SPACE_IO)) {
                        ioaddr = pciaddr & PCI_BASE_ADDRESS_IO_MASK;
                        if (check_region(ioaddr, chip_tbl[chip_idx].io_size))
                                continue;
                } else if ((ioaddr = (long)ioremap(pciaddr & PCI_BASE_ADDRESS_MEM_MASK,
                                                                                   chip_tbl[chip_idx].io_size)) == 0) {
                        printk(KERN_INFO "Failed to map PCI address %#x.\n",
                                   (int)pciaddr);
                        continue;
                }

                /* EPIC-specific code: Soft-reset the chip ere setting as master. */
                outl(0x0001, ioaddr + GENCTL);

                /* Activate the card: fix for brain-damaged Win98 BIOSes. */
                pcibios_read_config_word(pci_bus, pci_device_fn,
                                                                 PCI_COMMAND, &pci_command);
                new_command = pci_command | (pci_flags & 7);
                if (pci_command != new_command) {
                        printk(KERN_INFO "  The PCI BIOS has not enabled Ethernet"
                                   " device %4.4x-%4.4x."
                                   "  Updating PCI command %4.4x->%4.4x.\n",
                                   vendor, device, pci_command, new_command);
                        pcibios_write_config_word(pci_bus, pci_device_fn,
                                                                          PCI_COMMAND, new_command);
                }

                dev = chip_tbl[chip_idx].probe1(pci_bus, pci_device_fn, dev, ioaddr,
                                                                                irq, chip_idx, cards_found);
                /* Check the latency timer. */
                if (dev) {
                        u8 pci_latency;
                        pcibios_read_config_byte(pci_bus, pci_device_fn,
                                                                         PCI_LATENCY_TIMER, &pci_latency);
                        if (pci_latency < chip_tbl[chip_idx].min_latency) {
                                printk(KERN_INFO "  PCI latency timer (CFLT) value of %d is "
                                           "unreasonably low, setting to %d.\n", pci_latency,
                                           chip_tbl[chip_idx].min_latency);
                                pcibios_write_config_byte(pci_bus, pci_device_fn,
                                                                                  PCI_LATENCY_TIMER,
                                                                                  chip_tbl[chip_idx].min_latency);
                        }
                        dev = 0;
                        cards_found++;
                }
        }

        return cards_found ? 0 : -ENODEV;
}
#endif  /* not CARDBUS */

static struct device *epic_probe1(int pci_bus, int pci_devfn,
                                                                  struct device *dev, long ioaddr, int irq,
                                                                  int chip_idx, int card_idx)
{
        struct epic_private *ep;
        int i, option = 0, duplex = 0;

        if (dev && dev->mem_start) {
                option = dev->mem_start;
                duplex = (dev->mem_start & 16) ? 1 : 0;
        } else if (card_idx >= 0  &&  card_idx < MAX_UNITS) {
                if (options[card_idx] >= 0)
                        option = options[card_idx];
                if (full_duplex[card_idx] >= 0)
                        duplex = full_duplex[card_idx];
        }

        dev = init_etherdev(dev, 0);

        dev->base_addr = ioaddr;
        dev->irq = irq;
        printk(KERN_INFO "%s: %s at %#lx, IRQ %d, ",
                   dev->name, chip_tbl[chip_idx].name, ioaddr, dev->irq);

#if defined(HAS_PCI_NETIF)
        acpi_set_pwr_state(pci_bus, pci_devfn, ACPI_D0);
#endif
        /* Bring the chip out of low-power mode. */
        outl(0x4200, ioaddr + GENCTL);
        /* Magic?!  If we don't set this bit the MII interface won't work. */
        outl(0x0008, ioaddr + TEST1);

        /* Turn on the MII transceiver. */
        outl(0x12, ioaddr + MIICfg);
        if (chip_idx == 1)
                outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
        outl(0x0200, ioaddr + GENCTL);

        /* This could also be read from the EEPROM. */
        for (i = 0; i < 3; i++)
                ((u16 *)dev->dev_addr)[i] = le16_to_cpu(inw(ioaddr + LAN0 + i*4));

        for (i = 0; i < 5; i++)
                printk("%2.2x:", dev->dev_addr[i]);
        printk("%2.2x.\n", dev->dev_addr[i]);

        if (epic_debug > 2) {
                printk(KERN_DEBUG "%s: EEPROM contents\n", dev->name);
                for (i = 0; i < 64; i++)
                        printk(" %4.4x%s", read_eeprom(ioaddr, i),
                                   i % 16 == 15 ? "\n" : "");
        }

        /* We do a request_region() to register /proc/ioports info. */
        request_region(ioaddr, EPIC_TOTAL_SIZE, dev->name);

        /* The data structures must be quadword aligned. */
        ep = kmalloc(sizeof(*ep), GFP_KERNEL | GFP_DMA);
        memset(ep, 0, sizeof(*ep));
        dev->priv = ep;

        ep->next_module = root_epic_dev;
        root_epic_dev = dev;

        ep->pci_bus = pci_bus;
        ep->pci_dev_fn = pci_devfn;
        ep->chip_flags = chip_features[chip_idx];

        /* Find the connected MII xcvrs.
           Doing this in open() would allow detecting external xcvrs later, but
           takes too much time. */
        {
                int phy, phy_idx;
                for (phy = 1, phy_idx = 0; phy < 32 && phy_idx < sizeof(ep->phys);
                         phy++) {
                        int mii_status = mdio_read(ioaddr, phy, 1);
                        if (mii_status != 0xffff  && mii_status != 0x0000) {
                                ep->phys[phy_idx++] = phy;
                                printk(KERN_INFO "%s: MII transceiver #%d control "
                                           "%4.4x status %4.4x.\n"
                                           KERN_INFO "%s:  Autonegotiation advertising %4.4x "
                                           "link partner %4.4x.\n",
                                           dev->name, phy, mdio_read(ioaddr, phy, 0), mii_status,
                                           dev->name, mdio_read(ioaddr, phy, 4),
                                           mdio_read(ioaddr, phy, 5));
                        }
                }
                ep->mii_phy_cnt = phy_idx;
                if (phy_idx == 0) {
                        printk(KERN_WARNING "%s: ***WARNING***: No MII transceiver found!\n",
                                   dev->name);
                        /* Use the known PHY address of the EPII. */
                        ep->phys[0] = 3;
                }
        }

        /* Turn off the MII xcvr (175 only!), leave the chip in low-power mode. */
        if (ep->chip_flags & MII_PWRDWN)
                outl(inl(ioaddr + NVCTL) & ~0x483C, ioaddr + NVCTL);
        outl(0x0008, ioaddr + GENCTL);

        /* The lower four bits are the media type. */
        ep->force_fd = duplex;
        dev->if_port = ep->default_port = option;
        if (ep->default_port)
                ep->medialock = 1;

        /* The Epic-specific entries in the device structure. */
        dev->open = &epic_open;
        dev->hard_start_xmit = &epic_start_xmit;
        dev->stop = &epic_close;
        dev->get_stats = &epic_get_stats;
        dev->set_multicast_list = &set_rx_mode;
        dev->do_ioctl = &mii_ioctl;

        return dev;
}

/* Serial EEPROM section. */

/*  EEPROM_Ctrl bits. */
#define EE_SHIFT_CLK    0x04    /* EEPROM shift clock. */
#define EE_CS                   0x02    /* EEPROM chip select. */
#define EE_DATA_WRITE   0x08    /* EEPROM chip data in. */
#define EE_WRITE_0              0x01
#define EE_WRITE_1              0x09
#define EE_DATA_READ    0x10    /* EEPROM chip data out. */
#define EE_ENB                  (0x0001 | EE_CS)

/* Delay between EEPROM clock transitions.
   No extra delay is needed with 33Mhz PCI, but 66Mhz is untested.
 */

#define eeprom_delay()  inl(ee_addr)

/* The EEPROM commands include the alway-set leading bit. */
#define EE_WRITE_CMD    (5 << 6)
#define EE_READ64_CMD   (6 << 6)
#define EE_READ256_CMD  (6 << 8)
#define EE_ERASE_CMD    (7 << 6)

static int read_eeprom(long ioaddr, int location)
{
        int i;
        int retval = 0;
        long ee_addr = ioaddr + EECTL;
        int read_cmd = location |
                (inl(ee_addr) & 0x40 ? EE_READ64_CMD : EE_READ256_CMD);

        outl(EE_ENB & ~EE_CS, ee_addr);
        outl(EE_ENB, ee_addr);

        /* Shift the read command bits out. */
        for (i = 12; i >= 0; i--) {
                short dataval = (read_cmd & (1 << i)) ? EE_WRITE_1 : EE_WRITE_0;
                outl(EE_ENB | dataval, ee_addr);
                eeprom_delay();
                outl(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
                eeprom_delay();
        }
        outl(EE_ENB, ee_addr);

        for (i = 16; i > 0; i--) {
                outl(EE_ENB | EE_SHIFT_CLK, ee_addr);
                eeprom_delay();
                retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0);
                outl(EE_ENB, ee_addr);
                eeprom_delay();
        }

        /* Terminate the EEPROM access. */
        outl(EE_ENB & ~EE_CS, ee_addr);
        return retval;
}

#define MII_READOP              1
#define MII_WRITEOP             2
static int mdio_read(long ioaddr, int phy_id, int location)
{
        int i;

        outl((phy_id << 9) | (location << 4) | MII_READOP, ioaddr + MIICtrl);
        /* Typical operation takes < 50 ticks. */
        for (i = 4000; i > 0; i--)
                if ((inl(ioaddr + MIICtrl) & MII_READOP) == 0)
                        return inw(ioaddr + MIIData);
        return 0xffff;
}

static void mdio_write(long ioaddr, int phy_id, int location, int value)
{
        int i;

        outw(value, ioaddr + MIIData);
        outl((phy_id << 9) | (location << 4) | MII_WRITEOP, ioaddr + MIICtrl);
        for (i = 10000; i > 0; i--) {
                if ((inl(ioaddr + MIICtrl) & MII_WRITEOP) == 0)
                        break;
        }
        return;
}


static int
epic_open(struct device *dev)
{
        struct epic_private *ep = (struct epic_private *)dev->priv;
        long ioaddr = dev->base_addr;
        int i;

        ep->full_duplex = ep->force_fd;

        /* Soft reset the chip. */
        outl(0x4001, ioaddr + GENCTL);

        if (request_irq(dev->irq, &epic_interrupt, SA_SHIRQ, dev->name, dev))
                return -EAGAIN;

        MOD_INC_USE_COUNT;

        epic_init_ring(dev);

        outl(0x4000, ioaddr + GENCTL);
        /* This next magic! line by Ken Yamaguchi.. ?? */
        outl(0x0008, ioaddr + TEST1);

        /* Pull the chip out of low-power mode, enable interrupts, and set for
           PCI read multiple.  The MIIcfg setting and strange write order are
           required by the details of which bits are reset and the transceiver
           wiring on the Ositech CardBus card.
        */
        outl(0x12, ioaddr + MIICfg);
        if (ep->chip_flags & MII_PWRDWN)
                outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);

#if defined(__powerpc__) || defined(__sparc__)          /* Big endian */
        outl(0x4432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
        inl(ioaddr + GENCTL);
        outl(0x0432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
#else
        outl(0x4412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
        inl(ioaddr + GENCTL);
        outl(0x0412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
#endif

        for (i = 0; i < 3; i++)
                outl(cpu_to_le16(((u16*)dev->dev_addr)[i]), ioaddr + LAN0 + i*4);

        
        ep->tx_threshold = TX_FIFO_THRESH;
        outl(ep->tx_threshold, ioaddr + TxThresh);

        if (media2miictl[dev->if_port & 15]) {
                if (ep->mii_phy_cnt)
                        mdio_write(ioaddr, ep->phys[0], 0, media2miictl[dev->if_port&15]);
                if (dev->if_port == 1) {
                        if (epic_debug > 1)
                                printk(KERN_INFO "%s: Using the 10base2 transceiver, MII "
                                           "status %4.4x.\n",
                                           dev->name, mdio_read(ioaddr, ep->phys[0], 1));
                        outl(0x13, ioaddr + MIICfg);
                }
        } else {
                int mii_reg5 = mdio_read(ioaddr, ep->phys[0], 5);
                if (mii_reg5 != 0xffff) {
                        if ((mii_reg5 & 0x0100) || (mii_reg5 & 0x01C0) == 0x0040)
                                ep->full_duplex = 1;
                        else if (! (mii_reg5 & 0x4000))
                                mdio_write(ioaddr, ep->phys[0], 0, 0x1200);
                        if (epic_debug > 1)
                                printk(KERN_INFO "%s: Setting %s-duplex based on MII xcvr %d"
                                           " register read of %4.4x.\n", dev->name,
                                           ep->full_duplex ? "full" : "half",
                                           ep->phys[0], mii_reg5);
                }
        }

        outl(ep->full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
        outl(virt_to_bus(ep->rx_ring), ioaddr + PRxCDAR);
        outl(virt_to_bus(ep->tx_ring), ioaddr + PTxCDAR);

        /* Start the chip's Rx process. */
        set_rx_mode(dev);
        outl(StartRx | RxQueued, ioaddr + COMMAND);

        dev->tbusy = 0;
        dev->interrupt = 0;
        dev->start = 1;

        /* Enable interrupts by setting the interrupt mask. */
        outl((ep->chip_flags & TYPE2_INTR ? PCIBusErr175 : PCIBusErr170)
                 | CntFull | TxUnderrun | TxDone | TxEmpty
                 | RxError | RxOverflow | RxFull | RxHeader | RxDone,
                 ioaddr + INTMASK);

        if (epic_debug > 1)
                printk(KERN_DEBUG "%s: epic_open() ioaddr %lx IRQ %d status %4.4x "
                           "%s-duplex.\n",
                           dev->name, ioaddr, dev->irq, inl(ioaddr + GENCTL),
                           ep->full_duplex ? "full" : "half");

        /* Set the timer to switch to check for link beat and perhaps switch
           to an alternate media type. */
        init_timer(&ep->timer);
        ep->timer.expires = RUN_AT((24*HZ)/10);                 /* 2.4 sec. */
        ep->timer.data = (unsigned long)dev;
        ep->timer.function = &epic_timer;                               /* timer handler */
        add_timer(&ep->timer);

        return 0;
}

/* Reset the chip to recover from a PCI transaction error.
   This may occur at interrupt time. */
static void epic_pause(struct device *dev)
{
        long ioaddr = dev->base_addr;
        struct epic_private *ep = (struct epic_private *)dev->priv;

        /* Disable interrupts by clearing the interrupt mask. */
        outl(0x00000000, ioaddr + INTMASK);
        /* Stop the chip's Tx and Rx DMA processes. */
        outw(StopRx | StopTxDMA | StopRxDMA, ioaddr + COMMAND);

        /* Update the error counts. */
        if (inw(ioaddr + COMMAND) != 0xffff) {
                ep->stats.rx_missed_errors += inb(ioaddr + MPCNT);
                ep->stats.rx_frame_errors += inb(ioaddr + ALICNT);
                ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
        }

        /* Remove the packets on the Rx queue. */
        epic_rx(dev);
}

static void epic_restart(struct device *dev)
{
        long ioaddr = dev->base_addr;
        struct epic_private *ep = (struct epic_private *)dev->priv;
        int i;

        printk(KERN_DEBUG "%s: Restarting the EPIC chip, Rx %d/%d Tx %d/%d.\n",
                   dev->name, ep->cur_rx, ep->dirty_rx, ep->dirty_tx, ep->cur_tx);
        /* Soft reset the chip. */
        outl(0x0001, ioaddr + GENCTL);

        udelay(1);
        /* Duplicate code from epic_open(). */
        outl(0x0008, ioaddr + TEST1);

#if defined(__powerpc__) || defined(__sparc__)          /* Big endian */
        outl(0x0432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
#else
        outl(0x0412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
#endif
        outl(dev->if_port == 1 ? 0x13 : 0x12, ioaddr + MIICfg);
        if (ep->chip_flags & MII_PWRDWN)
                outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);

        for (i = 0; i < 3; i++)
                outl(cpu_to_le16(((u16*)dev->dev_addr)[i]), ioaddr + LAN0 + i*4);

        ep->tx_threshold = TX_FIFO_THRESH;
        outl(ep->tx_threshold, ioaddr + TxThresh);
        outl(ep->full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
        outl(virt_to_bus(&ep->rx_ring[ep->cur_rx%RX_RING_SIZE]), ioaddr + PRxCDAR);
        outl(virt_to_bus(&ep->tx_ring[ep->dirty_tx%TX_RING_SIZE]),
                 ioaddr + PTxCDAR);

        /* Start the chip's Rx process. */
        set_rx_mode(dev);
        outl(StartRx | RxQueued, ioaddr + COMMAND);

        /* Enable interrupts by setting the interrupt mask. */
        outl((ep->chip_flags & TYPE2_INTR ? PCIBusErr175 : PCIBusErr170)
                 | CntFull | TxUnderrun | TxDone | TxEmpty
                 | RxError | RxOverflow | RxFull | RxHeader | RxDone,
                 ioaddr + INTMASK);
        printk(KERN_DEBUG "%s: epic_restart() done, cmd status %4.4x, ctl %4.4x"
                   " interrupt %4.4x.\n",
                           dev->name, inl(ioaddr + COMMAND), inl(ioaddr + GENCTL),
                   inl(ioaddr + INTSTAT));
        return;
}

static void epic_timer(unsigned long data)
{
        struct device *dev = (struct device *)data;
        struct epic_private *ep = (struct epic_private *)dev->priv;
        long ioaddr = dev->base_addr;
        int next_tick = 60*HZ;
        int mii_reg5 = ep->mii_phy_cnt ? mdio_read(ioaddr, ep->phys[0], 5) : 0;

        if (epic_debug > 3) {
                printk(KERN_DEBUG "%s: Media monitor tick, Tx status %8.8x.\n",
                           dev->name, inl(ioaddr + TxSTAT));
                printk(KERN_DEBUG "%s: Other registers are IntMask %4.4x "
                           "IntStatus %4.4x RxStatus %4.4x.\n",
                           dev->name, inl(ioaddr + INTMASK), inl(ioaddr + INTSTAT),
                           inl(ioaddr + RxSTAT));
        }

        if (ep->cur_tx - ep->dirty_tx > TX_RING_SIZE/2  &&
                jiffies - dev->trans_start > TX_TIMEOUT) {
                printk(KERN_WARNING "%s: Tx hung, %d vs. %d.\n",
                           dev->name, ep->cur_tx, ep->dirty_tx);
                epic_tx_timeout(dev);
        }

        if (! ep->force_fd  &&  mii_reg5 != 0xffff) {
                int duplex = (mii_reg5&0x0100) || (mii_reg5 & 0x01C0) == 0x0040;
                if (ep->full_duplex != duplex) {
                        ep->full_duplex = duplex;
                        printk(KERN_INFO "%s: Setting %s-duplex based on MII #%d link"
                                   " partner capability of %4.4x.\n", dev->name,
                                   ep->full_duplex ? "full" : "half", ep->phys[0], mii_reg5);
                        outl(ep->full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
                }
        }

        ep->timer.expires = RUN_AT(next_tick);
        add_timer(&ep->timer);
}

static void epic_tx_timeout(struct device *dev)
{
        struct epic_private *ep = (struct epic_private *)dev->priv;
        long ioaddr = dev->base_addr;

        if (epic_debug > 0) {
                printk(KERN_WARNING "%s: Transmit timeout using MII device, "
                           "Tx status %4.4x.\n",
                           dev->name, inw(ioaddr + TxSTAT));
                if (epic_debug > 1) {
                        printk(KERN_DEBUG "%s: Tx indices: dirty_tx %d, cur_tx %d.\n",
                                   dev->name, ep->dirty_tx, ep->cur_tx);
                }
        }
        if (inw(ioaddr + TxSTAT) & 0x10) {              /* Tx FIFO underflow. */
                ep->stats.tx_fifo_errors++;
                outl(RestartTx, ioaddr + COMMAND);
        } else {
                epic_restart(dev);
                outl(TxQueued, dev->base_addr + COMMAND);
        }

        dev->trans_start = jiffies;
        ep->stats.tx_errors++;
        return;
}

/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
static void
epic_init_ring(struct device *dev)
{
        struct epic_private *ep = (struct epic_private *)dev->priv;
        int i;

        ep->tx_full = 0;
        ep->lock = (spinlock_t) SPIN_LOCK_UNLOCKED;
        ep->dirty_tx = ep->cur_tx = 0;
        ep->cur_rx = ep->dirty_rx = 0;
        ep->last_rx_time = jiffies;

        for (i = 0; i < RX_RING_SIZE; i++) {
                ep->rx_ring[i].status = 0x8000;         /* Owned by Epic chip */
                ep->rx_ring[i].buflength = PKT_BUF_SZ;
                {
                        /* Note the receive buffer must be longword aligned.
                           dev_alloc_skb() provides 16 byte alignment.  But do *not*
                           use skb_reserve() to align the IP header! */
                        struct sk_buff *skb;
                        skb = dev_alloc_skb(PKT_BUF_SZ);
                        ep->rx_skbuff[i] = skb;
                        if (skb == NULL)
                                break;                  /* Bad news!  */
                        skb->dev = dev;                 /* Mark as being used by this device. */
                        skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
                        ep->rx_ring[i].bufaddr = virt_to_bus(skb->tail);
                }
                ep->rx_ring[i].next = virt_to_bus(&ep->rx_ring[i+1]);
        }
        /* Mark the last entry as wrapping the ring. */
        ep->rx_ring[i-1].next = virt_to_bus(&ep->rx_ring[0]);

        /* The Tx buffer descriptor is filled in as needed, but we
           do need to clear the ownership bit. */
        for (i = 0; i < TX_RING_SIZE; i++) {
                ep->tx_skbuff[i] = 0;
                ep->tx_ring[i].status = 0x0000;
                ep->tx_ring[i].next = virt_to_bus(&ep->tx_ring[i+1]);
        }
        ep->tx_ring[i-1].next = virt_to_bus(&ep->tx_ring[0]);
}

static int
epic_start_xmit(struct sk_buff *skb, struct device *dev)
{
        struct epic_private *ep = (struct epic_private *)dev->priv;
        int entry, free_count;
        u32 ctrl_word;
        long flags;
        
        if(skb->len < ETH_ZLEN)
        {
                skb = skb_padto(skb, ETH_ZLEN);
                if(skb == NULL)
                        return 0;
        }

        /* Block a timer-based transmit from overlapping.  This could better be
           done with atomic_swap(1, dev->tbusy), but set_bit() works as well. */
        if (test_and_set_bit(0, (void*)&dev->tbusy) != 0) {
                if (jiffies - dev->trans_start > TX_TIMEOUT)
                        epic_tx_timeout(dev);
                return 1;
        }

        /* Caution: the write order is important here, set the base address
           with the "ownership" bits last. */

        /* Calculate the next Tx descriptor entry. */
        spin_lock_irqsave(&ep->lock, flags);
        free_count = ep->cur_tx - ep->dirty_tx;
        entry = ep->cur_tx++ % TX_RING_SIZE;

        ep->tx_skbuff[entry] = skb;
        ep->tx_ring[entry].txlength = (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN);
        ep->tx_ring[entry].bufaddr = virt_to_bus(skb->data);
        ep->tx_ring[entry].buflength = skb->len;

        if (free_count < TX_RING_SIZE/2) {/* Typical path */
                ctrl_word = 0x10; /* No interrupt */
        } else if (free_count == TX_RING_SIZE/2) {
                ctrl_word = 0x14; /* Tx-done intr. */
        } else if (free_count < TX_RING_SIZE - 1) {
                ctrl_word = 0x10; /* No Tx-done intr. */
        } else {
                /* Leave room for an additional entry. */
                ctrl_word = 0x14; /* Tx-done intr. */
                ep->tx_full = 1;
        }

        ep->tx_ring[entry].control = ctrl_word;
        ep->tx_ring[entry].status = 0x8000;     /* Pass ownership to the chip. */

        if ( ! ep->tx_full)
                clear_bit(0, (void*)&dev->tbusy);
        spin_unlock_irqrestore(&ep->lock, flags);
        /* Trigger an immediate transmit demand. */
        outl(TxQueued, dev->base_addr + COMMAND);

        dev->trans_start = jiffies;
        if (epic_debug > 4)
                printk(KERN_DEBUG "%s: Queued Tx packet size %d to slot %d, "
                           "flag %2.2x Tx status %8.8x.\n",
                           dev->name, (int)skb->len, entry, ctrl_word,
                           inl(dev->base_addr + TxSTAT));

        return 0;
}

/* The interrupt handler does all of the Rx thread work and cleans up
   after the Tx thread. */
static void epic_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
{
        struct device *dev = (struct device *)dev_instance;
        struct epic_private *ep = (struct epic_private *)dev->priv;
        long ioaddr = dev->base_addr;
        int status, boguscnt = max_interrupt_work;

#if defined(__i386__)
        /* A lock to prevent simultaneous entry bug on Intel SMP machines. */
        if (test_and_set_bit(0, (void*)&dev->interrupt)) {
                printk(KERN_ERR "%s: SMP simultaneous entry of an interrupt handler.\n",
                           dev->name);
                dev->interrupt = 0;     /* Avoid halting machine. */
                return;
        }
#else
        if (dev->interrupt) {
                printk(KERN_ERR "%s: Re-entering the interrupt handler.\n", dev->name);
                return;
        }
        dev->interrupt = 1;
#endif

        do {
                status = inl(ioaddr + INTSTAT);
                /* Acknowledge all of the current interrupt sources ASAP. */
                outl(status & 0x00007fff, ioaddr + INTSTAT);

                if (epic_debug > 4)
                        printk(KERN_DEBUG "%s: interrupt  interrupt=%#8.8x new "
                                   "intstat=%#8.8x.\n",
                                   dev->name, status, inl(ioaddr + INTSTAT));

                if ((status & IntrSummary) == 0)
                        break;

                if (status & (RxDone | RxStarted | RxEarlyWarn | RxOverflow))
                        epic_rx(dev);

                if (status & (TxEmpty | TxDone)) {
                        unsigned int dirty_tx, cur_tx;

                        /* Note: if this lock becomes a problem we can narrow the locked
                           region at the cost of occasionally grabbing the lock more
                           times. */
                        spin_lock(&ep->lock);
                        cur_tx = ep->cur_tx;
                        dirty_tx = ep->dirty_tx;
                        for (; cur_tx - dirty_tx > 0; dirty_tx++) {
                                int entry = dirty_tx % TX_RING_SIZE;
                                int txstatus = ep->tx_ring[entry].status;

                                if (txstatus < 0)
                                        break;                  /* It still hasn't been Txed */

                                if ( ! (txstatus & 0x0001)) {
                                        /* There was an major error, log it. */
#ifndef final_version
                                        if (epic_debug > 1)
                                                printk("%s: Transmit error, Tx status %8.8x.\n",
                                                           dev->name, txstatus);
#endif
                                        ep->stats.tx_errors++;
                                        if (txstatus & 0x1050) ep->stats.tx_aborted_errors++;
                                        if (txstatus & 0x0008) ep->stats.tx_carrier_errors++;
                                        if (txstatus & 0x0040) ep->stats.tx_window_errors++;
                                        if (txstatus & 0x0010) ep->stats.tx_fifo_errors++;
#ifdef ETHER_STATS
                                        if (txstatus & 0x1000) ep->stats.collisions16++;
#endif
                                } else {
#ifdef ETHER_STATS
                                        if ((txstatus & 0x0002) != 0) ep->stats.tx_deferred++;
#endif
                                        ep->stats.collisions += (txstatus >> 8) & 15;
                                        ep->stats.tx_packets++;
                                        ep->stats.tx_bytes += ep->tx_ring[entry].txlength;